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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Richard Sandiford > Sent: Friday, November 18, 2022 9:30 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw > ; Marcus Shawcroft > ; Kyrylo Tkachov > Subject: Re: [PATCH]AArch64 Fix vector re-interpretation between partial > SIMD modes >=20 > Richard Sandiford via Gcc-patches writes: > > Tamar Christina writes: > >> Hi All, > >> > >> While writing a patch series I started getting incorrect codegen out > >> from VEC_PERM on partial struct types. > >> > >> It turns out that this was happening because the > >> TARGET_CAN_CHANGE_MODE_CLASS implementation has a slight bug in > it. The hook only checked for SIMD to > >> Partial but never Partial to SIMD. This resulted in incorrect subreg= s to be > >> generated from the fallback code in VEC_PERM_EXPR expansions. > >> > >> I have unfortunately not been able to trigger it using a standalone > >> testcase as the mid-end optimizes away the permute every time I try > >> to describe a permute that would result in the bug. > >> > >> The patch now rejects any conversion of partial SIMD struct types, > >> unless they are both partial structures of the same number of > >> registers or one is a SIMD type who's size is less than 8 bytes. > >> > >> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > >> > >> Ok for master? And backport to GCC 12? > >> > >> Thanks, > >> Tamar > >> > >> gcc/ChangeLog: > >> > >> * config/aarch64/aarch64.cc (aarch64_can_change_mode_class): > Restrict > >> conversions between partial struct types properly. > >> > >> --- inline copy of patch -- > >> diff --git a/gcc/config/aarch64/aarch64.cc > >> b/gcc/config/aarch64/aarch64.cc index > >> > d3c3650d7d728f56adb65154127dc7b72386c5a7..84dbe2f4ea7d03b424602ed9 > 8a3 > >> 4e7824217dc91 100644 > >> --- a/gcc/config/aarch64/aarch64.cc > >> +++ b/gcc/config/aarch64/aarch64.cc > >> @@ -26471,9 +26471,10 @@ aarch64_can_change_mode_class > (machine_mode from, > >> bool from_pred_p =3D (from_flags & VEC_SVE_PRED); > >> bool to_pred_p =3D (to_flags & VEC_SVE_PRED); > >> > >> - bool from_full_advsimd_struct_p =3D (from_flags =3D=3D (VEC_ADVSIMD= | > VEC_STRUCT)); > >> bool to_partial_advsimd_struct_p =3D (to_flags =3D=3D (VEC_ADVSIMD = | > VEC_STRUCT > >> | VEC_PARTIAL)); > >> + bool from_partial_advsimd_struct_p =3D (from_flags =3D=3D (VEC_ADVS= IMD > | VEC_STRUCT > >> + | VEC_PARTIAL)); > >> > >> /* Don't allow changes between predicate modes and other modes. > >> Only predicate registers can hold predicate modes and only @@ > >> -26496,9 +26497,23 @@ aarch64_can_change_mode_class > (machine_mode from, > >> return false; > >> > >> /* Don't allow changes between partial and full Advanced SIMD > structure > >> - modes. */ > >> - if (from_full_advsimd_struct_p && to_partial_advsimd_struct_p) > >> - return false; > >> + modes unless both are a partial struct with the same number of > registers > >> + or the vector bitsizes must be the same. */ > >> + if (to_partial_advsimd_struct_p ^ from_partial_advsimd_struct_p) > >> + { > >> + /* If they're both partial structures, allow if they have the s= ame > number > >> + or registers. */ > >> + if (to_partial_advsimd_struct_p =3D=3D from_partial_advsimd_str= uct_p) > >> + return known_eq (GET_MODE_SIZE (from), GET_MODE_SIZE (to)); > > > > It looks like the ^ makes this line unreachable. I guess it should be > > a separate top-level condition. > > > >> + /* If one is a normal SIMD register, allow only if no larger th= an 64-bit. > */ > >> + if ((to_flags & VEC_ADVSIMD) =3D=3D to_flags) > >> + return known_le (GET_MODE_SIZE (to), 8); > >> + else if ((from_flags & VEC_ADVSIMD) =3D=3D from_flags) > >> + return known_le (GET_MODE_SIZE (from), 8); > >> + > >> + return false; > >> + } > > > > I don't think we need to restrict this to SIMD modes. A plain DI > > would be OK too. So I think it should just be: > > > > return (known_le (GET_MODE_SIZE (to), 8) > > || known_le (GET_MODE_SIZE (from, 8)); >=20 > Looking again, all the other tests return false if they found a definite = problem > and fall through to later code otherwise. I think we should do the same = here. I've rewritten the conditions. I needed to allow any conversions as long as= they're both partial vectors. There were various intrinsics tests that rely on for inst= ance being able to take a subreg of a VN2x8QI from a VN3x8QI for instance. I did not only all= ow the smaller case since it didn't seem logical to block paradoxical subregs of this kind= . Reload seems to be correctly handling them as separate 64-bit registers (we= have tests for this it looks like.) So Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? And backport to GCC 12? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_can_change_mode_class): Restrict conversions between partial struct types properly. ---- inline copy of patch --- diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index c91df6f5006c257690aafb75398933d628a970e1..ff02c78f895b26a70b2653e58db= 453f4b5870666 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -26658,9 +26658,10 @@ aarch64_can_change_mode_class (machine_mode from, bool from_pred_p =3D (from_flags & VEC_SVE_PRED); bool to_pred_p =3D (to_flags & VEC_SVE_PRED); =20 - bool from_full_advsimd_struct_p =3D (from_flags =3D=3D (VEC_ADVSIMD | VE= C_STRUCT)); bool to_partial_advsimd_struct_p =3D (to_flags =3D=3D (VEC_ADVSIMD | VEC= _STRUCT | VEC_PARTIAL)); + bool from_partial_advsimd_struct_p =3D (from_flags =3D=3D (VEC_ADVSIMD |= VEC_STRUCT + | VEC_PARTIAL)); =20 /* Don't allow changes between predicate modes and other modes. Only predicate registers can hold predicate modes and only @@ -26682,9 +26683,10 @@ aarch64_can_change_mode_class (machine_mode from, || GET_MODE_UNIT_SIZE (from) !=3D GET_MODE_UNIT_SIZE (to))) return false; =20 - /* Don't allow changes between partial and full Advanced SIMD structure - modes. */ - if (from_full_advsimd_struct_p && to_partial_advsimd_struct_p) + /* Don't allow changes between partial and other registers only if + one is a normal SIMD register, allow only if not larger than 64-bit. = */ + if ((to_partial_advsimd_struct_p ^ from_partial_advsimd_struct_p) + && (known_gt (GET_MODE_SIZE (to), 8) || known_gt (GET_MODE_SIZE (to)= , 8))) return false; =20 if (maybe_ne (BITS_PER_SVE_VECTOR, 128u)) --_002_VI1PR08MB53251BC306B3501ED8558D56FF149VI1PR08MB5325eurp_ Content-Type: application/octet-stream; name="rb16562.patch" Content-Description: rb16562.patch Content-Disposition: attachment; filename="rb16562.patch"; size=1527; creation-date="Thu, 01 Dec 2022 16:20:38 GMT"; modification-date="Thu, 01 Dec 2022 16:20:44 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmNjIGIvZ2NjL2NvbmZpZy9h YXJjaDY0L2FhcmNoNjQuY2MKaW5kZXggYzkxZGY2ZjUwMDZjMjU3NjkwYWFmYjc1Mzk4OTMzZDYy OGE5NzBlMS4uZmYwMmM3OGY4OTViMjZhNzBiMjY1M2U1OGRiNDUzZjRiNTg3MDY2NiAxMDA2NDQK LS0tIGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQuY2MKKysrIGIvZ2NjL2NvbmZpZy9hYXJj aDY0L2FhcmNoNjQuY2MKQEAgLTI2NjU4LDkgKzI2NjU4LDEwIEBAIGFhcmNoNjRfY2FuX2NoYW5n ZV9tb2RlX2NsYXNzIChtYWNoaW5lX21vZGUgZnJvbSwKICAgYm9vbCBmcm9tX3ByZWRfcCA9IChm cm9tX2ZsYWdzICYgVkVDX1NWRV9QUkVEKTsKICAgYm9vbCB0b19wcmVkX3AgPSAodG9fZmxhZ3Mg JiBWRUNfU1ZFX1BSRUQpOwogCi0gIGJvb2wgZnJvbV9mdWxsX2FkdnNpbWRfc3RydWN0X3AgPSAo ZnJvbV9mbGFncyA9PSAoVkVDX0FEVlNJTUQgfCBWRUNfU1RSVUNUKSk7CiAgIGJvb2wgdG9fcGFy dGlhbF9hZHZzaW1kX3N0cnVjdF9wID0gKHRvX2ZsYWdzID09IChWRUNfQURWU0lNRCB8IFZFQ19T VFJVQ1QKIAkJCQkJCSAgIHwgVkVDX1BBUlRJQUwpKTsKKyAgYm9vbCBmcm9tX3BhcnRpYWxfYWR2 c2ltZF9zdHJ1Y3RfcCA9IChmcm9tX2ZsYWdzID09IChWRUNfQURWU0lNRCB8IFZFQ19TVFJVQ1QK KwkJCQkJCSAgIHwgVkVDX1BBUlRJQUwpKTsKIAogICAvKiBEb24ndCBhbGxvdyBjaGFuZ2VzIGJl dHdlZW4gcHJlZGljYXRlIG1vZGVzIGFuZCBvdGhlciBtb2Rlcy4KICAgICAgT25seSBwcmVkaWNh dGUgcmVnaXN0ZXJzIGNhbiBob2xkIHByZWRpY2F0ZSBtb2RlcyBhbmQgb25seQpAQCAtMjY2ODIs OSArMjY2ODMsMTAgQEAgYWFyY2g2NF9jYW5fY2hhbmdlX21vZGVfY2xhc3MgKG1hY2hpbmVfbW9k ZSBmcm9tLAogCSAgfHwgR0VUX01PREVfVU5JVF9TSVpFIChmcm9tKSAhPSBHRVRfTU9ERV9VTklU X1NJWkUgKHRvKSkpCiAgICAgcmV0dXJuIGZhbHNlOwogCi0gIC8qIERvbid0IGFsbG93IGNoYW5n ZXMgYmV0d2VlbiBwYXJ0aWFsIGFuZCBmdWxsIEFkdmFuY2VkIFNJTUQgc3RydWN0dXJlCi0gICAg IG1vZGVzLiAgKi8KLSAgaWYgKGZyb21fZnVsbF9hZHZzaW1kX3N0cnVjdF9wICYmIHRvX3BhcnRp YWxfYWR2c2ltZF9zdHJ1Y3RfcCkKKyAgLyogRG9uJ3QgYWxsb3cgY2hhbmdlcyBiZXR3ZWVuIHBh cnRpYWwgYW5kIG90aGVyIHJlZ2lzdGVycyBvbmx5IGlmCisgICAgIG9uZSBpcyBhIG5vcm1hbCBT SU1EIHJlZ2lzdGVyLCBhbGxvdyBvbmx5IGlmIG5vdCBsYXJnZXIgdGhhbiA2NC1iaXQuICAqLwor ICBpZiAoKHRvX3BhcnRpYWxfYWR2c2ltZF9zdHJ1Y3RfcCBeIGZyb21fcGFydGlhbF9hZHZzaW1k X3N0cnVjdF9wKQorICAgICAgJiYgKGtub3duX2d0IChHRVRfTU9ERV9TSVpFICh0byksIDgpIHx8 IGtub3duX2d0IChHRVRfTU9ERV9TSVpFICh0byksIDgpKSkKICAgICByZXR1cm4gZmFsc2U7CiAK ICAgaWYgKG1heWJlX25lIChCSVRTX1BFUl9TVkVfVkVDVE9SLCAxMjh1KSkK --_002_VI1PR08MB53251BC306B3501ED8558D56FF149VI1PR08MB5325eurp_--