From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2087.outbound.protection.outlook.com [40.107.21.87]) by sourceware.org (Postfix) with ESMTPS id 88FDC3858C5F for ; Thu, 5 Oct 2023 18:18:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 88FDC3858C5F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/pl78/yuqk0cf9GIF4CZbymCHr7aL64/eJGCGubye4A=; b=uh7+OxoF/APdBmqFaP66vm+7tyDgTNosopGXIk1l/S3JFIAmKOoweihu2idzlo0qzWgzGcgeJUPmMir+4+6+sAhbj7gBIWFVSTpM8KtRNhQ7TbkkgJRHqAczGv8XyelrLmPlJvjvX7m7ayRX6XEOMlMfG2ofbc4K+lLd483kkQ8= Received: from AS4P189CA0017.EURP189.PROD.OUTLOOK.COM (2603:10a6:20b:5db::7) by PR3PR08MB5788.eurprd08.prod.outlook.com (2603:10a6:102:8b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.28; Thu, 5 Oct 2023 18:18:26 +0000 Received: from AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:5db:cafe::6) by AS4P189CA0017.outlook.office365.com (2603:10a6:20b:5db::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.29 via Frontend Transport; Thu, 5 Oct 2023 18:18:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT008.mail.protection.outlook.com (100.127.141.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.29 via Frontend Transport; Thu, 5 Oct 2023 18:18:26 +0000 Received: ("Tessian outbound fdf44c93bd44:v211"); Thu, 05 Oct 2023 18:18:25 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: ffc9db7ef452cda1 X-CR-MTA-TID: 64aa7808 Received: from 05b4702bfa96.3 by 64aa7808-outbound-1.mta.getcheckrecipient.com id ABAEF9B6-3128-4A51-9F5B-42234BAA1A9B.1; Thu, 05 Oct 2023 18:18:19 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 05b4702bfa96.3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 05 Oct 2023 18:18:19 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Cd6niD4ECk3NpCRVHHl22Hx3lXKlUkZ58IZuR2uTNk/JOa1ZKkkQA2AIECOTO9c/JlZaTGFTVjkv/MT4arKTNdp33VbqCct/9KTijN4LZGoMnZk8/IF+/DNFIsTn7L0thgFqgYvZ7j+eNZChN7/Dj1Oq9hgYlUDfD0rIbU8F2Wu5SwIJHcF26utctv7axk83faHRYVn01BX2DnaosycsuRZJ/U/QmUscWFHJ4zJk3uafX/ecJ8CHSZK5XUfZ8Yo+2BfQDQmbjJvbiP1Mfuh2+l9/XTCZvazddgYlh5aX/nLiQJo+0HYZBLo+0cJvR1CZtCZRvFm92gFKmXFN5ivz+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/pl78/yuqk0cf9GIF4CZbymCHr7aL64/eJGCGubye4A=; b=cdASGRFlQbXrqi2kPfofbnHypgYaBLCq7AWOOuuNYk61ebX82FoRIEbh4i7q2K2bK2fRjPp2yVXyn/njSTaQ9NcjdwboKclrkgs+U6K4ojD8jlMtbCbb9RTZrlIhFYlbugNGKGdQUa3dKbWttPACkz8BtqHfYta+p9FX9bmm+bKlWmsnHZoJMLrv1ez029HIapvgRFw4qBLojYo9h1e/D94QbT2wtF01Zqb+dkgNPEmhgkQZcxYW2S9ob9knxTfXPuvHBZJoVn6ErlVx0ZBxyzMsAwvkUowW/yalgJwK3Q59FEYxQma1sH1OVzc3Ik/mwqDl/174TsDiyUhwL8tU3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/pl78/yuqk0cf9GIF4CZbymCHr7aL64/eJGCGubye4A=; b=uh7+OxoF/APdBmqFaP66vm+7tyDgTNosopGXIk1l/S3JFIAmKOoweihu2idzlo0qzWgzGcgeJUPmMir+4+6+sAhbj7gBIWFVSTpM8KtRNhQ7TbkkgJRHqAczGv8XyelrLmPlJvjvX7m7ayRX6XEOMlMfG2ofbc4K+lLd483kkQ8= Received: from VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) by DU0PR08MB9203.eurprd08.prod.outlook.com (2603:10a6:10:417::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.29; Thu, 5 Oct 2023 18:18:16 +0000 Received: from VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::662f:8e26:1bf8:aaa1]) by VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::662f:8e26:1bf8:aaa1%7]) with mapi id 15.20.6838.033; Thu, 5 Oct 2023 18:18:15 +0000 From: Tamar Christina To: Richard Sandiford CC: "gcc-patches@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov Subject: RE: [PATCH]AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] Thread-Topic: [PATCH]AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] Thread-Index: AQHZ8NzlnfiIf3gzqEutRtLoRWPFYLAuekpsgA0T5BA= Date: Thu, 5 Oct 2023 18:18:15 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: VI1PR08MB5325:EE_|DU0PR08MB9203:EE_|AM7EUR03FT008:EE_|PR3PR08MB5788:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c188555-3fe5-48ee-138d-08dbc5cf77bf x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: kZ065wdsTXk2nhD3g9Bg552XmBgdtGdixAZHQClpAR88o67SP70NkdGY1xNu0n1kFqSFZ9sUpZE7v4iWbqEN/7omOURq82puvinG19QL6I3bs660TVdUtYIFLX5+upQEbhRip1sciNAmOz8JFxF9Yx7DBHuDFaatN5/hZ1JAlIB9vjqDA/7S0ba/9bq82JwbJwvis8YFH+ssj16ackJvX/5hE9OCMzQYZayWb2NB9PtpV96FE8ygdOdmEI0b23/lP4IClPxvdc8o9r6D28p1gz+POaaeZ606PBUF/SiTUuBqDfVA525V7J3Mu6pvzMlWBKZaBzxi8bANRLxanaBg0JDuCGPM70wK9XN8Iq+ffl+8IeZ/9T4TFRT+q2KEOB6UFGs/ISVEqZMIp8uzVVTWxB6tRFZtrjcQUlqwUzIxhOacJPcnksp7eXACy8F0OeSwRd2Mcd8lhasDiT9j6M9RhdIw66aTfySNDJtyQJywLqaxRLlspezKEqMwb/ryc4xmaa2YPHGLjEONp9a8AG8+/XtVTOnaOhiGMk/zZiPLYu3ZwWIbKllyrZS2kYgyqfor8wIgDWLdZHGUz/E2pg7h+SQPBpdbr4NMnB2suNtkYCv3T9GBxp1vNmt7itVn6Cnd4/WbK3S4TEsVTxopdgFdAQ== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR08MB5325.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(396003)(346002)(366004)(136003)(376002)(230922051799003)(64100799003)(186009)(451199024)(1800799009)(6636002)(316002)(8936002)(8676002)(30864003)(66476007)(66946007)(66556008)(66446008)(84970400001)(41300700001)(64756008)(54906003)(76116006)(83380400001)(2906002)(6862004)(5660300002)(4326008)(52536014)(478600001)(71200400001)(9686003)(55016003)(26005)(7696005)(6506007)(122000001)(99936003)(38070700005)(38100700002)(86362001)(33656002);DIR:OUT;SFP:1101; Content-Type: multipart/mixed; boundary="_002_VI1PR08MB53251FDBCDC1C958595E9F9CFFCAAVI1PR08MB5325eurp_" MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9203 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 8f7d99ab-eb3f-4d1b-1fa8-08dbc5cf71a3 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jl2v4haWpmu7SFbf/lFTmVo8xIvYJJ+r0Z5NksnZTQfjzUcfk8YWBmOwJBhuGU+H329vKniVhR89FgzGjRD5EUpQF8PjQAQ6lJLs7Nz/17sVpq6v8ZFl32Pu1fitsveIimFyXL0mlHP608BbOM+eTv2tmXevH1ZnuQpNitSfHxko9fC3rff1GeJMztg4vvhJGhKB4LPT1lHX+ubct7TOpmmWvOlfC/i7SJD8DkW0cJAQMNKs2XYvls33QUlI9OhRQ1FDtgkM2povIIm9vUwhnnRtlObG6VdcwXCpvmZNRLsqg6wOXqMsM2Yc/nczQeqEVlVEYtffOD9GxXiXqeIZ/IOs37Z95AlyimEb5QVHHEfKYsWUrhA8v6g+f9iMA2udIxnSIOXUnor3nDysTwSKMdryOHmTl0GC7aOGeP2eZj1283ENhSgV6DOWM+Fz+uxupA7+PUfDNnTAwikfD/nI79Dl2h2nZbnazcKuoiKO4MTmlSAzQjjNZ8q6vIJaVeQStFMiIU3zrtCs6YSyXJ1uBZwQsXVmXGGWDBFj99OKIqdAu0kFtRmb4t/8q7U5S6NNSiu4zQrOglbcIoghr1YJ2NE1E1mMS680fn/ruGK6gIr8p8Nvgm6U6+LsOD0oYSk5e/k21H4IlP+zSChpkP9TmWiw0yc0khGgUOEpYf0ztVUjuxrAPqealKnvzTtcgn6wt/73XtJpzRRPxE5zol8h3GE3iieNp+F3nZFHUjUZsHxa3iWJPEEdLVWMSBZrFnYOZt/ISlhJdUg4BfH+00tzXA== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(346002)(39860400002)(230922051799003)(1800799009)(451199024)(82310400011)(186009)(64100799003)(46966006)(36840700001)(40470700004)(316002)(336012)(36860700001)(55016003)(81166007)(99936003)(40460700003)(356005)(40480700001)(33656002)(86362001)(82740400003)(83380400001)(47076005)(41300700001)(54906003)(8676002)(4326008)(6862004)(5660300002)(52536014)(84970400001)(8936002)(2906002)(30864003)(26005)(70206006)(6636002)(70586007)(7696005)(235185007)(6506007)(9686003)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 18:18:26.0345 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c188555-3fe5-48ee-138d-08dbc5cf77bf X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5788 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,TXREP,T_SPF_TEMPERROR,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_002_VI1PR08MB53251FDBCDC1C958595E9F9CFFCAAVI1PR08MB5325eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, > The lowpart_subreg should simplify this back into CONST0_RTX (mode), > making it no different from: >=20 > emti_move_insn (target, CONST0_RTX (mode)); >=20 > If the intention is to share zeros between modes (sounds good!), then I t= hink > the subreg needs to be on the lhs instead. >=20 > > + rtx neg =3D lowpart_subreg (V2DFmode, target, mode); > > + emit_insn (gen_negv2df2 (neg, lowpart_subreg (V2DFmode, target, > > + mode))); >=20 > The rhs seems simpler as copy_rtx (neg). (Even the copy_rtx shouldn't be > needed after RA, but it's probably more future-proof to keep it.) >=20 > > + emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode)); >=20 > This shouldn't be needed, since neg is already a reference to target. >=20 > Overall, looks like a nice change/framework. Updated the patch, and in te process also realized this can be used for the vector variants: Hi All, This adds a way to generate special sequences for creation of constants for which we don't have single instructions sequences which would have normally lead to a GP -> FP transfer or a literal load. The patch starts out by adding support for creating 1 << 63 using fneg (mov= 0). Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p, aarch64_maybe_generate_simd_constant): New. * config/aarch64/aarch64-simd.md (*aarch64_simd_mov, *aarch64_simd_mov): Add new coden for special constants. * config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int): Take optional mode. (aarch64_simd_special_constant_p, aarch64_maybe_generate_simd_constant): New. * config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for special constants. * config/aarch64/constraints.md (Dx): new. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/fneg-abs_1.c: Updated. * gcc.target/aarch64/fneg-abs_2.c: Updated. * gcc.target/aarch64/fneg-abs_4.c: Updated. * gcc.target/aarch64/dbl_mov_immediate_1.c: Updated. --- inline copy of patch --- diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch= 64-protos.h index 60a55f4bc1956786ea687fc7cad7ec9e4a84e1f0..36d6c688bc888a51a9de174bd36= 65aebe891b8b1 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -831,6 +831,8 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_im= mediate_info *); bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *, enum simd_immediate_check w =3D AARCH64_CHECK_MOV); rtx aarch64_check_zero_based_sve_index_immediate (rtx); +bool aarch64_maybe_generate_simd_constant (rtx, rtx, machine_mode); +bool aarch64_simd_special_constant_p (rtx, machine_mode); bool aarch64_sve_index_immediate_p (rtx); bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool); bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index 81ff5bad03d598fa0d48df93d172a28bc0d1d92e..33eceb436584ff73c7271f93639= f2246d1af19e0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -142,26 +142,35 @@ (define_insn "aarch64_dup_lane_" [(set_attr "type" "neon_dup")] ) =20 -(define_insn "*aarch64_simd_mov" +(define_insn_and_split "*aarch64_simd_mov" [(set (match_operand:VDMOV 0 "nonimmediate_operand") (match_operand:VDMOV 1 "general_operand"))] "TARGET_FLOAT && (register_operand (operands[0], mode) || aarch64_simd_reg_or_zero (operands[1], mode))" - {@ [cons: =3D0, 1; attrs: type, arch] - [w , m ; neon_load1_1reg , * ] ldr\t%d0, %1 - [r , m ; load_8 , * ] ldr\t%x0, %1 - [m , Dz; store_8 , * ] str\txzr, %0 - [m , w ; neon_store1_1reg, * ] str\t%d1, %0 - [m , r ; store_8 , * ] str\t%x1, %0 - [w , w ; neon_logic , simd] mov\t%0., %1. - [w , w ; neon_logic , * ] fmov\t%d0, %d1 - [?r, w ; neon_to_gp , simd] umov\t%0, %1.d[0] - [?r, w ; neon_to_gp , * ] fmov\t%x0, %d1 - [?w, r ; f_mcr , * ] fmov\t%d0, %1 - [?r, r ; mov_reg , * ] mov\t%0, %1 - [w , Dn; neon_move , simd] << aarch64_output_simd_mov_immedi= ate (operands[1], 64); - [w , Dz; f_mcr , * ] fmov\t%d0, xzr + {@ [cons: =3D0, 1; attrs: type, arch, length] + [w , m ; neon_load1_1reg , * , *] ldr\t%d0, %1 + [r , m ; load_8 , * , *] ldr\t%x0, %1 + [m , Dz; store_8 , * , *] str\txzr, %0 + [m , w ; neon_store1_1reg, * , *] str\t%d1, %0 + [m , r ; store_8 , * , *] str\t%x1, %0 + [w , w ; neon_logic , simd, *] mov\t%0., %1. + [w , w ; neon_logic , * , *] fmov\t%d0, %d1 + [?r, w ; neon_to_gp , simd, *] umov\t%0, %1.d[0] + [?r, w ; neon_to_gp , * , *] fmov\t%x0, %d1 + [?w, r ; f_mcr , * , *] fmov\t%d0, %1 + [?r, r ; mov_reg , * , *] mov\t%0, %1 + [w , Dn; neon_move , simd, *] << aarch64_output_simd_mov_imm= ediate (operands[1], 64); + [w , Dz; f_mcr , * , *] fmov\t%d0, xzr + [w , Dx; neon_move , simd, 8] # + } + "CONST_INT_P (operands[1]) + && aarch64_simd_special_constant_p (operands[1], mode) + && FP_REGNUM_P (REGNO (operands[0]))" + [(const_int 0)] + { + aarch64_maybe_generate_simd_constant (operands[0], operands[1], = mode); + DONE; } ) =20 @@ -181,19 +190,30 @@ (define_insn_and_split "*aarch64_simd_mov= " [?r , r ; multiple , * , 8] # [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_im= mediate (operands[1], 128); [w , Dz; fmov , * , 4] fmov\t%d0, xzr + [w , Dx; neon_move , simd, 8] # } "&& reload_completed - && (REG_P (operands[0]) + && ((REG_P (operands[0]) && REG_P (operands[1]) && !(FP_REGNUM_P (REGNO (operands[0])) - && FP_REGNUM_P (REGNO (operands[1]))))" + && FP_REGNUM_P (REGNO (operands[1])))) + || (aarch64_simd_special_constant_p (operands[1], mode) + && FP_REGNUM_P (REGNO (operands[0]))))" [(const_int 0)] { if (GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) aarch64_simd_emit_reg_reg_move (operands, DImode, 2); else - aarch64_split_simd_move (operands[0], operands[1]); + { + if (FP_REGNUM_P (REGNO (operands[0])) + && mode =3D=3D V2DImode + && aarch64_maybe_generate_simd_constant (operands[0], operands[1], + mode)) + ; + else + aarch64_split_simd_move (operands[0], operands[1]); + } DONE; } ) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 9fbfc548a891f5d11940c6fd3c49a14bfbdec886..c5cf42f7801b291754840dcc5b3= 04577e8e0d391 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -11873,16 +11873,18 @@ aarch64_get_condition_code_1 (machine_mode mode, = enum rtx_code comp_code) /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector duplicate of such constants. If so, store in RET_WI the wide_int representation of the constant paired with the inner mode of the vector= mode - or TImode for scalar X constants. */ + or MODE for scalar X constants. If MODE is not provided then TImode is + used. */ =20 static bool -aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi) +aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi, + scalar_mode mode =3D TImode) { rtx elt =3D unwrap_const_vec_duplicate (x); if (!CONST_SCALAR_INT_P (elt)) return false; scalar_mode smode - =3D CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x)); + =3D CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x)); *ret_wi =3D rtx_mode_t (elt, smode); return true; } @@ -11931,6 +11933,49 @@ aarch64_const_vec_all_same_in_range_p (rtx x, && IN_RANGE (INTVAL (elt), minval, maxval)); } =20 +/* Some constants can't be made using normal mov instructions in Advanced = SIMD + but we can still create them in various ways. If the constant in VAL c= an be + created using alternate methods then if possible then return true and + additionally set TARGET to the rtx for the sequence if TARGET is not NU= LL. + Otherwise return false if sequence is not possible. */ + +bool +aarch64_maybe_generate_simd_constant (rtx target, rtx val, machine_mode mo= de) +{ + wide_int wval; + auto smode =3D GET_MODE_INNER (mode); + if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode)) + return false; + + /* For Advanced SIMD we can create an integer with only the top bit set + using fneg (0.0f). */ + if (TARGET_SIMD + && !TARGET_SVE + && smode =3D=3D DImode + && wi::only_sign_bit_p (wval)) + { + if (!target) + return true; + + /* Use the same base type as aarch64_gen_shareable_zero. */ + rtx zero =3D CONST0_RTX (V4SImode); + emit_move_insn (lowpart_subreg (V4SImode, target, mode), zero); + rtx neg =3D lowpart_subreg (V2DFmode, target, mode); + emit_insn (gen_negv2df2 (neg, copy_rtx (neg))); + return true; + } + + return false; +} + +/* Check if the value in VAL with mode MODE can be created using special + instruction sequences. */ + +bool aarch64_simd_special_constant_p (rtx val, machine_mode mode) +{ + return aarch64_maybe_generate_simd_constant (NULL_RTX, val, mode); +} + bool aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val) { diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 32c7adc89281b249b52ecedf2f1678749c289d18..6f7a6cd1830e5b7cdb3eab76f31= 43964278a8561 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1341,13 +1341,21 @@ (define_insn_and_split "*movdi_aarch64" [r, w ; f_mrc , fp , 4] fmov\t%x0, %d1 [w, w ; fmov , fp , 4] fmov\t%d0, %d1 [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immedi= ate (operands[1], DImode); - } - "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), D= Imode) - && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))" + [w, Dx ; neon_move, simd, 8] # + } + "CONST_INT_P (operands[1]) + && REG_P (operands[0]) + && ((!aarch64_move_imm (INTVAL (operands[1]), DImode) + && GP_REGNUM_P (REGNO (operands[0]))) + || (aarch64_simd_special_constant_p (operands[1], DImode) + && FP_REGNUM_P (REGNO (operands[0]))))" [(const_int 0)] { + if (GP_REGNUM_P (REGNO (operands[0]))) aarch64_expand_mov_immediate (operands[0], operands[1]); - DONE; + else + aarch64_maybe_generate_simd_constant (operands[0], operands[1], DImo= de); + DONE; } ) =20 diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constra= ints.md index 371a00827d84d8ea4a06ba2b00a761d3b179ae90..b3922bcb9a8b362c995c96c6d1c= 6eef034990251 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -488,6 +488,14 @@ (define_constraint "Dr" (and (match_code "const,const_vector") (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), false)"))) + +(define_constraint "Dx" + "@internal + A constraint that matches a vector of 64-bit immediates which we don't ha= ve a + single instruction to create but that we can create in creative ways." + (and (match_code "const_int,const,const_vector") + (match_test "aarch64_simd_special_constant_p (op, DImode)"))) + (define_constraint "Dz" "@internal A constraint that matches a vector of immediate zero." diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/t= estsuite/gcc.target/aarch64/dbl_mov_immediate_1.c index ba6a230457ba7a86f1939665fe9177ecdb45f935..fb9088e9d2849c0ea10a8741795= 181a0543c3cb2 100644 --- a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c +++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c @@ -48,6 +48,8 @@ double d4(void) =20 /* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" = 1 } } */ /* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" = 1 } } */ -/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808= " 1 } } */ -/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" = 2 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808= " 0 } } */ +/* { dg-final { scan-assembler-times {movi\tv[0-9]+.2d, #0} 1 } } */ +/* { dg-final { scan-assembler-times {fneg\tv[0-9]+.2d, v[0-9]+.2d} 1 } } = */ +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" = 1 } } */ =20 diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/= gcc.target/aarch64/fneg-abs_1.c index f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686= e88465cd8482a 100644 --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c @@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a) =20 /* ** t3: -** adrp x0, .LC[0-9]+ -** ldr q[0-9]+, \[x0, #:lo12:.LC0\] +** movi v[0-9]+.4s, 0 +** fneg v[0-9]+.2d, v[0-9]+.2d ** orr v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/= gcc.target/aarch64/fneg-abs_2.c index 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d= 777d3046a9f78 100644 --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c @@ -20,8 +20,8 @@ float32_t f1 (float32_t a) =20 /* ** f2: -** mov x0, -9223372036854775808 -** fmov d[0-9]+, x0 +** fmov d[0-9]+, xzr +** fneg v[0-9]+.2d, v[0-9]+.2d ** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b ** ret */ @@ -29,3 +29,4 @@ float64_t f2 (float64_t a) { return -fabs (a); } + diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/= gcc.target/aarch64/fneg-abs_4.c index 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34= f142f53d8242c 100644 --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c @@ -8,8 +8,8 @@ =20 /* ** negabs: -** mov x0, -9223372036854775808 -** fmov d[0-9]+, x0 +** fmov d[0-9]+, xzr +** fneg v[0-9]+.2d, v[0-9]+.2d ** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b ** ret */ --_002_VI1PR08MB53251FDBCDC1C958595E9F9CFFCAAVI1PR08MB5325eurp_ Content-Type: application/octet-stream; name="rb17722.patch" Content-Description: rb17722.patch Content-Disposition: attachment; filename="rb17722.patch"; size=12402; creation-date="Thu, 05 Oct 2023 18:18:11 GMT"; modification-date="Thu, 05 Oct 2023 18:18:15 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LXByb3Rvcy5oIGIvZ2NjL2Nv bmZpZy9hYXJjaDY0L2FhcmNoNjQtcHJvdG9zLmgKaW5kZXggNjBhNTVmNGJjMTk1Njc4NmVhNjg3 ZmM3Y2FkN2VjOWU0YTg0ZTFmMC4uMzZkNmM2ODhiYzg4OGE1MWE5ZGUxNzRiZDM2NjVhZWJlODkx YjhiMSAxMDA2NDQKLS0tIGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQtcHJvdG9zLmgKKysr IGIvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQtcHJvdG9zLmgKQEAgLTgzMSw2ICs4MzEsOCBA QCBib29sIGFhcmNoNjRfc3ZlX3B0cnVlX3N2cGF0dGVybl9wIChydHgsIHN0cnVjdCBzaW1kX2lt bWVkaWF0ZV9pbmZvICopOwogYm9vbCBhYXJjaDY0X3NpbWRfdmFsaWRfaW1tZWRpYXRlIChydHgs IHN0cnVjdCBzaW1kX2ltbWVkaWF0ZV9pbmZvICosCiAJCQllbnVtIHNpbWRfaW1tZWRpYXRlX2No ZWNrIHcgPSBBQVJDSDY0X0NIRUNLX01PVik7CiBydHggYWFyY2g2NF9jaGVja196ZXJvX2Jhc2Vk X3N2ZV9pbmRleF9pbW1lZGlhdGUgKHJ0eCk7Citib29sIGFhcmNoNjRfbWF5YmVfZ2VuZXJhdGVf c2ltZF9jb25zdGFudCAocnR4LCBydHgsIG1hY2hpbmVfbW9kZSk7Citib29sIGFhcmNoNjRfc2lt ZF9zcGVjaWFsX2NvbnN0YW50X3AgKHJ0eCwgbWFjaGluZV9tb2RlKTsKIGJvb2wgYWFyY2g2NF9z dmVfaW5kZXhfaW1tZWRpYXRlX3AgKHJ0eCk7CiBib29sIGFhcmNoNjRfc3ZlX2FyaXRoX2ltbWVk aWF0ZV9wIChtYWNoaW5lX21vZGUsIHJ0eCwgYm9vbCk7CiBib29sIGFhcmNoNjRfc3ZlX3NxYWRk X3Nxc3ViX2ltbWVkaWF0ZV9wIChtYWNoaW5lX21vZGUsIHJ0eCwgYm9vbCk7CmRpZmYgLS1naXQg YS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC1zaW1kLm1kIGIvZ2NjL2NvbmZpZy9hYXJjaDY0 L2FhcmNoNjQtc2ltZC5tZAppbmRleCA4MWZmNWJhZDAzZDU5OGZhMGQ0OGRmOTNkMTcyYTI4YmMw ZDFkOTJlLi4zM2VjZWI0MzY1ODRmZjczYzcyNzFmOTM2MzlmMjI0NmQxYWYxOWUwIDEwMDY0NAot LS0gYS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC1zaW1kLm1kCisrKyBiL2djYy9jb25maWcv YWFyY2g2NC9hYXJjaDY0LXNpbWQubWQKQEAgLTE0MiwyNiArMTQyLDM1IEBAIChkZWZpbmVfaW5z biAiYWFyY2g2NF9kdXBfbGFuZV88dnN3YXBfd2lkdGhfbmFtZT48bW9kZT4iCiAgIFsoc2V0X2F0 dHIgInR5cGUiICJuZW9uX2R1cDxxPiIpXQogKQogCi0oZGVmaW5lX2luc24gIiphYXJjaDY0X3Np bWRfbW92PFZETU9WOm1vZGU+IgorKGRlZmluZV9pbnNuX2FuZF9zcGxpdCAiKmFhcmNoNjRfc2lt ZF9tb3Y8VkRNT1Y6bW9kZT4iCiAgIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZETU9WIDAgIm5vbmlt bWVkaWF0ZV9vcGVyYW5kIikKIAkobWF0Y2hfb3BlcmFuZDpWRE1PViAxICJnZW5lcmFsX29wZXJh bmQiKSldCiAgICJUQVJHRVRfRkxPQVQKICAgICYmIChyZWdpc3Rlcl9vcGVyYW5kIChvcGVyYW5k c1swXSwgPE1PREU+bW9kZSkKICAgICAgICB8fCBhYXJjaDY0X3NpbWRfcmVnX29yX3plcm8gKG9w ZXJhbmRzWzFdLCA8TU9ERT5tb2RlKSkiCi0gIHtAIFtjb25zOiA9MCwgMTsgYXR0cnM6IHR5cGUs IGFyY2hdCi0gICAgIFt3ICwgbSA7IG5lb25fbG9hZDFfMXJlZzxxPiAsICogICBdIGxkclx0JWQw LCAlMQotICAgICBbciAsIG0gOyBsb2FkXzggICAgICAgICAgICAgLCAqICAgXSBsZHJcdCV4MCwg JTEKLSAgICAgW20gLCBEejsgc3RvcmVfOCAgICAgICAgICAgICwgKiAgIF0gc3RyXHR4enIsICUw Ci0gICAgIFttICwgdyA7IG5lb25fc3RvcmUxXzFyZWc8cT4sICogICBdIHN0clx0JWQxLCAlMAot ICAgICBbbSAsIHIgOyBzdG9yZV84ICAgICAgICAgICAgLCAqICAgXSBzdHJcdCV4MSwgJTAKLSAg ICAgW3cgLCB3IDsgbmVvbl9sb2dpYzxxPiAgICAgICwgc2ltZF0gbW92XHQlMC48VmJ0eXBlPiwg JTEuPFZidHlwZT4KLSAgICAgW3cgLCB3IDsgbmVvbl9sb2dpYzxxPiAgICAgICwgKiAgIF0gZm1v dlx0JWQwLCAlZDEKLSAgICAgWz9yLCB3IDsgbmVvbl90b19ncDxxPiAgICAgICwgc2ltZF0gdW1v dlx0JTAsICUxLmRbMF0KLSAgICAgWz9yLCB3IDsgbmVvbl90b19ncDxxPiAgICAgICwgKiAgIF0g Zm1vdlx0JXgwLCAlZDEKLSAgICAgWz93LCByIDsgZl9tY3IgICAgICAgICAgICAgICwgKiAgIF0g Zm1vdlx0JWQwLCAlMQotICAgICBbP3IsIHIgOyBtb3ZfcmVnICAgICAgICAgICAgLCAqICAgXSBt b3ZcdCUwLCAlMQotICAgICBbdyAsIERuOyBuZW9uX21vdmU8cT4gICAgICAgLCBzaW1kXSA8PCBh YXJjaDY0X291dHB1dF9zaW1kX21vdl9pbW1lZGlhdGUgKG9wZXJhbmRzWzFdLCA2NCk7Ci0gICAg IFt3ICwgRHo7IGZfbWNyICAgICAgICAgICAgICAsICogICBdIGZtb3ZcdCVkMCwgeHpyCisgIHtA IFtjb25zOiA9MCwgMTsgYXR0cnM6IHR5cGUsIGFyY2gsIGxlbmd0aF0KKyAgICAgW3cgLCBtIDsg bmVvbl9sb2FkMV8xcmVnPHE+ICwgKiAgICwgKl0gbGRyXHQlZDAsICUxCisgICAgIFtyICwgbSA7 IGxvYWRfOCAgICAgICAgICAgICAsICogICAsICpdIGxkclx0JXgwLCAlMQorICAgICBbbSAsIER6 OyBzdG9yZV84ICAgICAgICAgICAgLCAqICAgLCAqXSBzdHJcdHh6ciwgJTAKKyAgICAgW20gLCB3 IDsgbmVvbl9zdG9yZTFfMXJlZzxxPiwgKiAgICwgKl0gc3RyXHQlZDEsICUwCisgICAgIFttICwg ciA7IHN0b3JlXzggICAgICAgICAgICAsICogICAsICpdIHN0clx0JXgxLCAlMAorICAgICBbdyAs IHcgOyBuZW9uX2xvZ2ljPHE+ICAgICAgLCBzaW1kLCAqXSBtb3ZcdCUwLjxWYnR5cGU+LCAlMS48 VmJ0eXBlPgorICAgICBbdyAsIHcgOyBuZW9uX2xvZ2ljPHE+ICAgICAgLCAqICAgLCAqXSBmbW92 XHQlZDAsICVkMQorICAgICBbP3IsIHcgOyBuZW9uX3RvX2dwPHE+ICAgICAgLCBzaW1kLCAqXSB1 bW92XHQlMCwgJTEuZFswXQorICAgICBbP3IsIHcgOyBuZW9uX3RvX2dwPHE+ICAgICAgLCAqICAg LCAqXSBmbW92XHQleDAsICVkMQorICAgICBbP3csIHIgOyBmX21jciAgICAgICAgICAgICAgLCAq ICAgLCAqXSBmbW92XHQlZDAsICUxCisgICAgIFs/ciwgciA7IG1vdl9yZWcgICAgICAgICAgICAs ICogICAsICpdIG1vdlx0JTAsICUxCisgICAgIFt3ICwgRG47IG5lb25fbW92ZTxxPiAgICAgICAs IHNpbWQsICpdIDw8IGFhcmNoNjRfb3V0cHV0X3NpbWRfbW92X2ltbWVkaWF0ZSAob3BlcmFuZHNb MV0sIDY0KTsKKyAgICAgW3cgLCBEejsgZl9tY3IgICAgICAgICAgICAgICwgKiAgICwgKl0gZm1v dlx0JWQwLCB4enIKKyAgICAgW3cgLCBEeDsgbmVvbl9tb3ZlICAgICAgICAgICwgc2ltZCwgOF0g IworICB9CisgICJDT05TVF9JTlRfUCAob3BlcmFuZHNbMV0pCisgICAmJiBhYXJjaDY0X3NpbWRf c3BlY2lhbF9jb25zdGFudF9wIChvcGVyYW5kc1sxXSwgPE1PREU+bW9kZSkKKyAgICYmIEZQX1JF R05VTV9QIChSRUdOTyAob3BlcmFuZHNbMF0pKSIKKyAgWyhjb25zdF9pbnQgMCldCisgIHsKKyAg ICBhYXJjaDY0X21heWJlX2dlbmVyYXRlX3NpbWRfY29uc3RhbnQgKG9wZXJhbmRzWzBdLCBvcGVy YW5kc1sxXSwgPE1PREU+bW9kZSk7CisgICAgRE9ORTsKICAgfQogKQogCkBAIC0xODEsMTkgKzE5 MCwzMCBAQCAoZGVmaW5lX2luc25fYW5kX3NwbGl0ICIqYWFyY2g2NF9zaW1kX21vdjxWUU1PVjpt b2RlPiIKICAgICAgWz9yICwgciA7IG11bHRpcGxlICAgICAgICAgICAsICogICAsIDhdICMKICAg ICAgW3cgICwgRG47IG5lb25fbW92ZTxxPiAgICAgICAsIHNpbWQsIDRdIDw8IGFhcmNoNjRfb3V0 cHV0X3NpbWRfbW92X2ltbWVkaWF0ZSAob3BlcmFuZHNbMV0sIDEyOCk7CiAgICAgIFt3ICAsIER6 OyBmbW92ICAgICAgICAgICAgICAgLCAqICAgLCA0XSBmbW92XHQlZDAsIHh6cgorICAgICBbdyAg LCBEeDsgbmVvbl9tb3ZlICAgICAgICAgICwgc2ltZCwgOF0gIwogICB9CiAgICImJiByZWxvYWRf Y29tcGxldGVkCi0gICAmJiAoUkVHX1AgKG9wZXJhbmRzWzBdKQorICAgJiYgKChSRUdfUCAob3Bl cmFuZHNbMF0pCiAJJiYgUkVHX1AgKG9wZXJhbmRzWzFdKQogCSYmICEoRlBfUkVHTlVNX1AgKFJF R05PIChvcGVyYW5kc1swXSkpCi0JICAgICAmJiBGUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJhbmRz WzFdKSkpKSIKKwkgICAgICYmIEZQX1JFR05VTV9QIChSRUdOTyAob3BlcmFuZHNbMV0pKSkpCisg ICAgICAgfHwgKGFhcmNoNjRfc2ltZF9zcGVjaWFsX2NvbnN0YW50X3AgKG9wZXJhbmRzWzFdLCA8 TU9ERT5tb2RlKQorCSAgICYmIEZQX1JFR05VTV9QIChSRUdOTyAob3BlcmFuZHNbMF0pKSkpIgog ICBbKGNvbnN0X2ludCAwKV0KICAgewogICAgIGlmIChHUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJh bmRzWzBdKSkKIAkmJiBHUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJhbmRzWzFdKSkpCiAgICAgICBh YXJjaDY0X3NpbWRfZW1pdF9yZWdfcmVnX21vdmUgKG9wZXJhbmRzLCBESW1vZGUsIDIpOwogICAg IGVsc2UKLSAgICAgIGFhcmNoNjRfc3BsaXRfc2ltZF9tb3ZlIChvcGVyYW5kc1swXSwgb3BlcmFu ZHNbMV0pOworICAgICAgeworCWlmIChGUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJhbmRzWzBdKSkK KwkgICAgJiYgPE1PREU+bW9kZSA9PSBWMkRJbW9kZQorCSAgICAmJiBhYXJjaDY0X21heWJlX2dl bmVyYXRlX3NpbWRfY29uc3RhbnQgKG9wZXJhbmRzWzBdLCBvcGVyYW5kc1sxXSwKKwkJCQkJCSAg ICAgPE1PREU+bW9kZSkpCisJICA7CisJZWxzZQorCSAgYWFyY2g2NF9zcGxpdF9zaW1kX21vdmUg KG9wZXJhbmRzWzBdLCBvcGVyYW5kc1sxXSk7CisgICAgICB9CiAgICAgRE9ORTsKICAgfQogKQpk aWZmIC0tZ2l0IGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQuY2MgYi9nY2MvY29uZmlnL2Fh cmNoNjQvYWFyY2g2NC5jYwppbmRleCA5ZmJmYzU0OGE4OTFmNWQxMTk0MGM2ZmQzYzQ5YTE0YmZi ZGVjODg2Li5jNWNmNDJmNzgwMWIyOTE3NTQ4NDBkY2M1YjMwNDU3N2U4ZTBkMzkxIDEwMDY0NAot LS0gYS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC5jYworKysgYi9nY2MvY29uZmlnL2FhcmNo NjQvYWFyY2g2NC5jYwpAQCAtMTE4NzMsMTYgKzExODczLDE4IEBAIGFhcmNoNjRfZ2V0X2NvbmRp dGlvbl9jb2RlXzEgKG1hY2hpbmVfbW9kZSBtb2RlLCBlbnVtIHJ0eF9jb2RlIGNvbXBfY29kZSkK IC8qIFJldHVybiB0cnVlIGlmIFggaXMgYSBDT05TVF9JTlQsIENPTlNUX1dJREVfSU5UIG9yIGEg Y29uc3RhbnQgdmVjdG9yCiAgICBkdXBsaWNhdGUgb2Ygc3VjaCBjb25zdGFudHMuICBJZiBzbywg c3RvcmUgaW4gUkVUX1dJIHRoZSB3aWRlX2ludAogICAgcmVwcmVzZW50YXRpb24gb2YgdGhlIGNv bnN0YW50IHBhaXJlZCB3aXRoIHRoZSBpbm5lciBtb2RlIG9mIHRoZSB2ZWN0b3IgbW9kZQotICAg b3IgVEltb2RlIGZvciBzY2FsYXIgWCBjb25zdGFudHMuICAqLworICAgb3IgTU9ERSBmb3Igc2Nh bGFyIFggY29uc3RhbnRzLiAgSWYgTU9ERSBpcyBub3QgcHJvdmlkZWQgdGhlbiBUSW1vZGUgaXMK KyAgIHVzZWQuICAqLwogCiBzdGF0aWMgYm9vbAotYWFyY2g2NF9leHRyYWN0X3ZlY19kdXBsaWNh dGVfd2lkZV9pbnQgKHJ0eCB4LCB3aWRlX2ludCAqcmV0X3dpKQorYWFyY2g2NF9leHRyYWN0X3Zl Y19kdXBsaWNhdGVfd2lkZV9pbnQgKHJ0eCB4LCB3aWRlX2ludCAqcmV0X3dpLAorCQkJCQlzY2Fs YXJfbW9kZSBtb2RlID0gVEltb2RlKQogewogICBydHggZWx0ID0gdW53cmFwX2NvbnN0X3ZlY19k dXBsaWNhdGUgKHgpOwogICBpZiAoIUNPTlNUX1NDQUxBUl9JTlRfUCAoZWx0KSkKICAgICByZXR1 cm4gZmFsc2U7CiAgIHNjYWxhcl9tb2RlIHNtb2RlCi0gICAgPSBDT05TVF9TQ0FMQVJfSU5UX1Ag KHgpID8gVEltb2RlIDogR0VUX01PREVfSU5ORVIgKEdFVF9NT0RFICh4KSk7CisgICAgPSBDT05T VF9TQ0FMQVJfSU5UX1AgKHgpID8gbW9kZSA6IEdFVF9NT0RFX0lOTkVSIChHRVRfTU9ERSAoeCkp OwogICAqcmV0X3dpID0gcnR4X21vZGVfdCAoZWx0LCBzbW9kZSk7CiAgIHJldHVybiB0cnVlOwog fQpAQCAtMTE5MzEsNiArMTE5MzMsNDkgQEAgYWFyY2g2NF9jb25zdF92ZWNfYWxsX3NhbWVfaW5f cmFuZ2VfcCAocnR4IHgsCiAJICAmJiBJTl9SQU5HRSAoSU5UVkFMIChlbHQpLCBtaW52YWwsIG1h eHZhbCkpOwogfQogCisvKiBTb21lIGNvbnN0YW50cyBjYW4ndCBiZSBtYWRlIHVzaW5nIG5vcm1h bCBtb3YgaW5zdHJ1Y3Rpb25zIGluIEFkdmFuY2VkIFNJTUQKKyAgIGJ1dCB3ZSBjYW4gc3RpbGwg Y3JlYXRlIHRoZW0gaW4gdmFyaW91cyB3YXlzLiAgSWYgdGhlIGNvbnN0YW50IGluIFZBTCBjYW4g YmUKKyAgIGNyZWF0ZWQgdXNpbmcgYWx0ZXJuYXRlIG1ldGhvZHMgdGhlbiBpZiBwb3NzaWJsZSB0 aGVuIHJldHVybiB0cnVlIGFuZAorICAgYWRkaXRpb25hbGx5IHNldCBUQVJHRVQgdG8gdGhlIHJ0 eCBmb3IgdGhlIHNlcXVlbmNlIGlmIFRBUkdFVCBpcyBub3QgTlVMTC4KKyAgIE90aGVyd2lzZSBy ZXR1cm4gZmFsc2UgaWYgc2VxdWVuY2UgaXMgbm90IHBvc3NpYmxlLiAgKi8KKworYm9vbAorYWFy Y2g2NF9tYXliZV9nZW5lcmF0ZV9zaW1kX2NvbnN0YW50IChydHggdGFyZ2V0LCBydHggdmFsLCBt YWNoaW5lX21vZGUgbW9kZSkKK3sKKyAgd2lkZV9pbnQgd3ZhbDsKKyAgYXV0byBzbW9kZSA9IEdF VF9NT0RFX0lOTkVSIChtb2RlKTsKKyAgaWYgKCFhYXJjaDY0X2V4dHJhY3RfdmVjX2R1cGxpY2F0 ZV93aWRlX2ludCAodmFsLCAmd3ZhbCwgc21vZGUpKQorICAgIHJldHVybiBmYWxzZTsKKworICAv KiBGb3IgQWR2YW5jZWQgU0lNRCB3ZSBjYW4gY3JlYXRlIGFuIGludGVnZXIgd2l0aCBvbmx5IHRo ZSB0b3AgYml0IHNldAorICAgICB1c2luZyBmbmVnICgwLjBmKS4gICovCisgIGlmIChUQVJHRVRf U0lNRAorICAgICAgJiYgIVRBUkdFVF9TVkUKKyAgICAgICYmIHNtb2RlID09IERJbW9kZQorICAg ICAgJiYgd2k6Om9ubHlfc2lnbl9iaXRfcCAod3ZhbCkpCisgICAgeworICAgICAgaWYgKCF0YXJn ZXQpCisJcmV0dXJuIHRydWU7CisKKyAgICAgIC8qIFVzZSB0aGUgc2FtZSBiYXNlIHR5cGUgYXMg YWFyY2g2NF9nZW5fc2hhcmVhYmxlX3plcm8uICAqLworICAgICAgcnR4IHplcm8gPSBDT05TVDBf UlRYIChWNFNJbW9kZSk7CisgICAgICBlbWl0X21vdmVfaW5zbiAobG93cGFydF9zdWJyZWcgKFY0 U0ltb2RlLCB0YXJnZXQsIG1vZGUpLCB6ZXJvKTsKKyAgICAgIHJ0eCBuZWcgPSBsb3dwYXJ0X3N1 YnJlZyAoVjJERm1vZGUsIHRhcmdldCwgbW9kZSk7CisgICAgICBlbWl0X2luc24gKGdlbl9uZWd2 MmRmMiAobmVnLCBjb3B5X3J0eCAobmVnKSkpOworICAgICAgcmV0dXJuIHRydWU7CisgICAgfQor CisgIHJldHVybiBmYWxzZTsKK30KKworLyogQ2hlY2sgaWYgdGhlIHZhbHVlIGluIFZBTCB3aXRo IG1vZGUgTU9ERSBjYW4gYmUgY3JlYXRlZCB1c2luZyBzcGVjaWFsCisgICBpbnN0cnVjdGlvbiBz ZXF1ZW5jZXMuICAqLworCitib29sIGFhcmNoNjRfc2ltZF9zcGVjaWFsX2NvbnN0YW50X3AgKHJ0 eCB2YWwsIG1hY2hpbmVfbW9kZSBtb2RlKQoreworICByZXR1cm4gYWFyY2g2NF9tYXliZV9nZW5l cmF0ZV9zaW1kX2NvbnN0YW50IChOVUxMX1JUWCwgdmFsLCBtb2RlKTsKK30KKwogYm9vbAogYWFy Y2g2NF9jb25zdF92ZWNfYWxsX3NhbWVfaW50X3AgKHJ0eCB4LCBIT1NUX1dJREVfSU5UIHZhbCkK IHsKZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0Lm1kIGIvZ2NjL2NvbmZp Zy9hYXJjaDY0L2FhcmNoNjQubWQKaW5kZXggMzJjN2FkYzg5MjgxYjI0OWI1MmVjZWRmMmYxNjc4 NzQ5YzI4OWQxOC4uNmY3YTZjZDE4MzBlNWI3Y2RiM2VhYjc2ZjMxNDM5NjQyNzhhODU2MSAxMDA2 NDQKLS0tIGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQubWQKKysrIGIvZ2NjL2NvbmZpZy9h YXJjaDY0L2FhcmNoNjQubWQKQEAgLTEzNDEsMTMgKzEzNDEsMjEgQEAgKGRlZmluZV9pbnNuX2Fu ZF9zcGxpdCAiKm1vdmRpX2FhcmNoNjQiCiAgICAgIFtyLCB3ICA7IGZfbXJjICAgICwgZnAgICwg NF0gZm1vdlx0JXgwLCAlZDEKICAgICAgW3csIHcgIDsgZm1vdiAgICAgLCBmcCAgLCA0XSBmbW92 XHQlZDAsICVkMQogICAgICBbdywgRGQgOyBuZW9uX21vdmUsIHNpbWQsIDRdIDw8IGFhcmNoNjRf b3V0cHV0X3NjYWxhcl9zaW1kX21vdl9pbW1lZGlhdGUgKG9wZXJhbmRzWzFdLCBESW1vZGUpOwot ICB9Ci0gICJDT05TVF9JTlRfUCAob3BlcmFuZHNbMV0pICYmICFhYXJjaDY0X21vdmVfaW1tIChJ TlRWQUwgKG9wZXJhbmRzWzFdKSwgREltb2RlKQotICAgJiYgUkVHX1AgKG9wZXJhbmRzWzBdKSAm JiBHUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJhbmRzWzBdKSkiCisgICAgIFt3LCBEeCA7IG5lb25f bW92ZSwgc2ltZCwgOF0gIworICB9CisgICJDT05TVF9JTlRfUCAob3BlcmFuZHNbMV0pCisgICAm JiBSRUdfUCAob3BlcmFuZHNbMF0pCisgICAmJiAoKCFhYXJjaDY0X21vdmVfaW1tIChJTlRWQUwg KG9wZXJhbmRzWzFdKSwgREltb2RlKQorCSYmIEdQX1JFR05VTV9QIChSRUdOTyAob3BlcmFuZHNb MF0pKSkKKyAgICAgICB8fCAoYWFyY2g2NF9zaW1kX3NwZWNpYWxfY29uc3RhbnRfcCAob3BlcmFu ZHNbMV0sIERJbW9kZSkKKwkgICAmJiBGUF9SRUdOVU1fUCAoUkVHTk8gKG9wZXJhbmRzWzBdKSkp KSIKICAgWyhjb25zdF9pbnQgMCldCiAgIHsKKyAgICBpZiAoR1BfUkVHTlVNX1AgKFJFR05PIChv cGVyYW5kc1swXSkpKQogICAgICAgYWFyY2g2NF9leHBhbmRfbW92X2ltbWVkaWF0ZSAob3BlcmFu ZHNbMF0sIG9wZXJhbmRzWzFdKTsKLSAgICAgIERPTkU7CisgICAgZWxzZQorICAgICAgYWFyY2g2 NF9tYXliZV9nZW5lcmF0ZV9zaW1kX2NvbnN0YW50IChvcGVyYW5kc1swXSwgb3BlcmFuZHNbMV0s IERJbW9kZSk7CisgICAgRE9ORTsKICAgfQogKQogCmRpZmYgLS1naXQgYS9nY2MvY29uZmlnL2Fh cmNoNjQvY29uc3RyYWludHMubWQgYi9nY2MvY29uZmlnL2FhcmNoNjQvY29uc3RyYWludHMubWQK aW5kZXggMzcxYTAwODI3ZDg0ZDhlYTRhMDZiYTJiMDBhNzYxZDNiMTc5YWU5MC4uYjM5MjJiY2I5 YThiMzYyYzk5NWM5NmM2ZDFjNmVlZjAzNDk5MDI1MSAxMDA2NDQKLS0tIGEvZ2NjL2NvbmZpZy9h YXJjaDY0L2NvbnN0cmFpbnRzLm1kCisrKyBiL2djYy9jb25maWcvYWFyY2g2NC9jb25zdHJhaW50 cy5tZApAQCAtNDg4LDYgKzQ4OCwxNCBAQCAoZGVmaW5lX2NvbnN0cmFpbnQgIkRyIgogIChhbmQg KG1hdGNoX2NvZGUgImNvbnN0LGNvbnN0X3ZlY3RvciIpCiAgICAgICAobWF0Y2hfdGVzdCAiYWFy Y2g2NF9zaW1kX3NoaWZ0X2ltbV9wIChvcCwgR0VUX01PREUgKG9wKSwKIAkJCQkJCSBmYWxzZSki KSkpCisKKyhkZWZpbmVfY29uc3RyYWludCAiRHgiCisgICJAaW50ZXJuYWwKKyBBIGNvbnN0cmFp bnQgdGhhdCBtYXRjaGVzIGEgdmVjdG9yIG9mIDY0LWJpdCBpbW1lZGlhdGVzIHdoaWNoIHdlIGRv bid0IGhhdmUgYQorIHNpbmdsZSBpbnN0cnVjdGlvbiB0byBjcmVhdGUgYnV0IHRoYXQgd2UgY2Fu IGNyZWF0ZSBpbiBjcmVhdGl2ZSB3YXlzLiIKKyAoYW5kIChtYXRjaF9jb2RlICJjb25zdF9pbnQs Y29uc3QsY29uc3RfdmVjdG9yIikKKyAgICAgIChtYXRjaF90ZXN0ICJhYXJjaDY0X3NpbWRfc3Bl Y2lhbF9jb25zdGFudF9wIChvcCwgREltb2RlKSIpKSkKKwogKGRlZmluZV9jb25zdHJhaW50ICJE eiIKICAgIkBpbnRlcm5hbAogIEEgY29uc3RyYWludCB0aGF0IG1hdGNoZXMgYSB2ZWN0b3Igb2Yg aW1tZWRpYXRlIHplcm8uIgpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fh cmNoNjQvZGJsX21vdl9pbW1lZGlhdGVfMS5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fh cmNoNjQvZGJsX21vdl9pbW1lZGlhdGVfMS5jCmluZGV4IGJhNmEyMzA0NTdiYTdhODZmMTkzOTY2 NWZlOTE3N2VjZGI0NWY5MzUuLmZiOTA4OGU5ZDI4NDljMGVhMTBhODc0MTc5NTE4MWEwNTQzYzNj YjIgMTAwNjQ0Ci0tLSBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2RibF9tb3Zf aW1tZWRpYXRlXzEuYworKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9kYmxf bW92X2ltbWVkaWF0ZV8xLmMKQEAgLTQ4LDYgKzQ4LDggQEAgZG91YmxlIGQ0KHZvaWQpCiAKIC8q IHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyAibW92XHR4XFswLTlcXSssIDI1ODM4 NTIzMjUyNzM2IiAgICAgICAxIH0gfSAqLwogLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVy LXRpbWVzICJtb3ZrXHR4XFswLTlcXSssIDB4NDBmZSwgbHNsIDQ4IiAgICAgIDEgfSB9ICovCi0v KiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMgIm1vdlx0eFxbMC05XF0rLCAtOTIy MzM3MjAzNjg1NDc3NTgwOCIgMSB9IH0gKi8KLS8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxl ci10aW1lcyAiZm1vdlx0ZFxbMC05XF0rLCB4XFswLTlcXSsiICAgICAgICAgICAyIH0gfSAqLwor LyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzICJtb3ZcdHhcWzAtOVxdKywgLTky MjMzNzIwMzY4NTQ3NzU4MDgiIDAgfSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJs ZXItdGltZXMge21vdmlcdHZbMC05XSsuMmQsICMwfSAxIH0gfSAqLworLyogeyBkZy1maW5hbCB7 IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtmbmVnXHR2WzAtOV0rLjJkLCB2WzAtOV0rLjJkfSAxIH0g fSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzICJmbW92XHRkXFswLTlc XSssIHhcWzAtOVxdKyIgICAgICAgICAgIDEgfSB9ICovCiAKZGlmZiAtLWdpdCBhL2djYy90ZXN0 c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2ZuZWctYWJzXzEuYyBiL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hYXJjaDY0L2ZuZWctYWJzXzEuYwppbmRleCBmODIzMDEzYzNkZGY2YjNhMjY2YzNh YmZjYmYyNjQyZmMyYTc1ZmE2Li40M2MzN2UyMWI1MGUxM2MwOWI4ZDY4NTA2ODZlODg0NjVjZDg0 ODJhIDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9mbmVnLWFi c18xLmMKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvZm5lZy1hYnNfMS5j CkBAIC0yOCw4ICsyOCw4IEBAIGZsb2F0MzJ4NF90IHQyIChmbG9hdDMyeDRfdCBhKQogCiAvKgog KiogdDM6Ci0qKglhZHJwCXgwLCAuTENbMC05XSsKLSoqCWxkcglxWzAtOV0rLCBcW3gwLCAjOmxv MTI6LkxDMFxdCisqKgltb3ZpCXZbMC05XSsuNHMsIDAKKyoqCWZuZWcJdlswLTldKy4yZCwgdlsw LTldKy4yZAogKioJb3JyCXZbMC05XSsuMTZiLCB2WzAtOV0rLjE2YiwgdlswLTldKy4xNmIKICoq CXJldAogKi8KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2Zu ZWctYWJzXzIuYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2ZuZWctYWJzXzIu YwppbmRleCAxNDExMjExNzZiMzA5ZTRiMmFhNDEzZGM1NTI3MWE2ZTNjOTNkNWUxLi5mYjE0ZWMz ZTIyMTBlMGZlZWZmODBmMjQxMGQ3NzdkMzA0NmE5Zjc4IDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1 aXRlL2djYy50YXJnZXQvYWFyY2g2NC9mbmVnLWFic18yLmMKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9n Y2MudGFyZ2V0L2FhcmNoNjQvZm5lZy1hYnNfMi5jCkBAIC0yMCw4ICsyMCw4IEBAIGZsb2F0MzJf dCBmMSAoZmxvYXQzMl90IGEpCiAKIC8qCiAqKiBmMjoKLSoqCW1vdgl4MCwgLTkyMjMzNzIwMzY4 NTQ3NzU4MDgKLSoqCWZtb3YJZFswLTldKywgeDAKKyoqCWZtb3YJZFswLTldKywgeHpyCisqKglm bmVnCXZbMC05XSsuMmQsIHZbMC05XSsuMmQKICoqCW9ycgl2WzAtOV0rLjhiLCB2WzAtOV0rLjhi LCB2WzAtOV0rLjhiCiAqKglyZXQKICovCkBAIC0yOSwzICsyOSw0IEBAIGZsb2F0NjRfdCBmMiAo ZmxvYXQ2NF90IGEpCiB7CiAgIHJldHVybiAtZmFicyAoYSk7CiB9CisKZGlmZiAtLWdpdCBhL2dj Yy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2ZuZWctYWJzXzQuYyBiL2djYy90ZXN0c3Vp dGUvZ2NjLnRhcmdldC9hYXJjaDY0L2ZuZWctYWJzXzQuYwppbmRleCAxMDg3OWRlYTc0NDYyZDM0 YjI2MTYwZWViMGJkNTRlYWQwNjMxNjZiLi40ZWEwMTA1ZjZjMGE5NzU2MDcwYmNjNjBkMzRmMTQy ZjUzZDgyNDJjIDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9m bmVnLWFic180LmMKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvZm5lZy1h YnNfNC5jCkBAIC04LDggKzgsOCBAQAogCiAvKgogKiogbmVnYWJzOgotKioJbW92CXgwLCAtOTIy MzM3MjAzNjg1NDc3NTgwOAotKioJZm1vdglkWzAtOV0rLCB4MAorKioJZm1vdglkWzAtOV0rLCB4 enIKKyoqCWZuZWcJdlswLTldKy4yZCwgdlswLTldKy4yZAogKioJb3JyCXZbMC05XSsuOGIsIHZb MC05XSsuOGIsIHZbMC05XSsuOGIKICoqCXJldAogKi8K --_002_VI1PR08MB53251FDBCDC1C958595E9F9CFFCAAVI1PR08MB5325eurp_--