From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-eopbgr70045.outbound.protection.outlook.com [40.107.7.45]) by sourceware.org (Postfix) with ESMTPS id C6D6C386EC0C for ; Fri, 11 Nov 2022 14:40:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C6D6C386EC0C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=PCZqHAesWWjW/VmbmKLLTiHWxW519LrqoZk/TBivrDcdKRtR0umgRL7JbiGekenJNBNPF4dcr2ZTvmfU2eMYtaeVCRhn2uy8afd+yfjvvu+zC5xP0uWowEyH4bdRZqCxO2XKPA4BrVC8DWA45Vqia6D0kc3NwvuuWPfESdNi+CZ+2AOoe6H9fMPpZtdbkUeGpR6UnU8abMQnYraJn2pUjLj32ytZn70R0nlGWT8i4b6bP5CHjlRauSp1eLTetkRmgr4KU4tfzJ37yXvxRSt3YABLzaeKDqYnoK/ZPpNKc5ht7pbvL3XKlk0CmeOAZ3Vnbhdx+vKhEYa9oikVmr9X9g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lgpt725tQogeB3eNGZsb3vupVsTyLZscev4MKARM5AI=; b=gN8V95T03V53+quYDuK8+D7/nhH1VN1w8jALNKBK/tpfpXGIgJxGoavmx/FDaMf350Fwkaiqaf4Snn6k9ss+jgbEgtghT9b8DlTfh0axxEjNXdf+ccqanG2CI3PgHqfGnPpvqOKn9foRHwDFbsxZ4NNnl4Fzyg9EASWxYi2AuFoDmKpv0MqaS4Ygb9xRoFsORYVRMWRE/TezvrutxHtjlDGCHUS7j8m+ATMyEulRRQ76caGz7mlFkV6qzIeOehvBgMG+bRoiBzHOy8NawPuJ7YHzY2PsADt3Iw3mqtG7wuTYNKYI2Kf0KKWN4ycB1fiNaN+1tU/zELuRlLVeoEX0Uw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lgpt725tQogeB3eNGZsb3vupVsTyLZscev4MKARM5AI=; b=WCRgE+qyt6+tiOTWMM6e0aWv352cCqBrHMpl3aYrGm9UzqvY0IJx6CZ+wiXGgJLpq62YQloaU2kYi1oCIUCFUqw6wY/x5Gq9IYAdtbeI/cidhUmfFjzlF8MP6me2MK9RM+HWiWaGT5xdBULL463eq2/VIr6EIu0QeHz1z64Kq9Y= Received: from DB6PR0601CA0029.eurprd06.prod.outlook.com (2603:10a6:4:17::15) by AS2PR08MB8974.eurprd08.prod.outlook.com (2603:10a6:20b:5fa::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 14:40:11 +0000 Received: from DBAEUR03FT012.eop-EUR03.prod.protection.outlook.com (2603:10a6:4:17:cafe::ff) by DB6PR0601CA0029.outlook.office365.com (2603:10a6:4:17::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13 via Frontend Transport; Fri, 11 Nov 2022 14:40:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT012.mail.protection.outlook.com (100.127.142.126) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.12 via Frontend Transport; Fri, 11 Nov 2022 14:40:10 +0000 Received: ("Tessian outbound 6c699027a257:v130"); Fri, 11 Nov 2022 14:40:10 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 0a695a1bc5168494 X-CR-MTA-TID: 64aa7808 Received: from bc52e4b36561.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id C3980610-B708-4CDE-98AA-13BB4CC11ED9.1; Fri, 11 Nov 2022 14:40:01 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id bc52e4b36561.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 11 Nov 2022 14:40:01 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RpPUQaFfE3E+/+NVp0Pcf0N4V9jazUCL7gNZQNh4lGJZZkO0O5+w4yDip/I8YECurUaIvhrWwXL3b1FSr9HYyao64azBqt4fOdkDbzIqqahcNxMuiYEolsp/Fa/jdp8DEODONhcv1PdCsW2//8qAU/g8dVQxQ0R62RKLmLLU4116jyWlNzSr09DeFTDOxwaASEanG6cEvFZgB+rJILdmt8o82GrePlxFhFDqU3ETbK/ZdnHW9ve8Fagu1e/0KZP2vvPtVORCU1qtKpdcIkJocdOSdyjjr174NAEcVh/CXdZai8xar4NMIW2CnDOPvuto1YsBPEiysnLzkTUKbAb+iQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lgpt725tQogeB3eNGZsb3vupVsTyLZscev4MKARM5AI=; b=Ip8HoFXDN4C6S7kFXoxL11cnHSDKjan1KvAzCrbGQwD3Mg1h567odpGydeAGQzvFY1erh1o48VtoMzD7u/SBmrQ+YVEQIcKtwTWBj/AAb9QZ6yGdEk7LVFB9xa7jQ2EBEqyWEWwX+VBA3jy2mWCIPE76mTUncFAziI6MEd/pOvrEtCryLY6b9ksdPmrvfs7ch4QTcdV++Aeky61sIA6SJFSKnlYtcWMBqqMs91QNETjAnUwkjWhyXNPXGI4Sz4Eu4rnAEqZ5Nq/QdS7yfmc/rdk21hQrOjID24t732y5mRmT2ArNOlw5ZCdsTq00TA716fBAlqjvYZTW3VQtMkr9fA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lgpt725tQogeB3eNGZsb3vupVsTyLZscev4MKARM5AI=; b=WCRgE+qyt6+tiOTWMM6e0aWv352cCqBrHMpl3aYrGm9UzqvY0IJx6CZ+wiXGgJLpq62YQloaU2kYi1oCIUCFUqw6wY/x5Gq9IYAdtbeI/cidhUmfFjzlF8MP6me2MK9RM+HWiWaGT5xdBULL463eq2/VIr6EIu0QeHz1z64Kq9Y= Received: from VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) by PAVPR08MB9553.eurprd08.prod.outlook.com (2603:10a6:102:314::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 14:39:55 +0000 Received: from VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::bd2a:aff9:b1a0:2fc7]) by VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::bd2a:aff9:b1a0:2fc7%4]) with mapi id 15.20.5813.013; Fri, 11 Nov 2022 14:39:54 +0000 From: Tamar Christina To: Richard Sandiford CC: "gcc-patches@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov Subject: RE: [PATCH 5/8]AArch64 aarch64: Make existing V2HF be usable. Thread-Topic: [PATCH 5/8]AArch64 aarch64: Make existing V2HF be usable. Thread-Index: AQHY7SAlWreqI6axPUuXHMahz+7ngK4qKs2fgA+wqFA= Date: Fri, 11 Nov 2022 14:39:54 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-ts-tracking-id: E57A0B9977E7B14DA1945A0513B49518.0 Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: VI1PR08MB5325:EE_|PAVPR08MB9553:EE_|DBAEUR03FT012:EE_|AS2PR08MB8974:EE_ X-MS-Office365-Filtering-Correlation-Id: 25e9a035-017e-40bc-72cc-08dac3f2a2eb x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: F84IpEzjOOt3hhuLsaHsfrQBn4LDTd4ZRJkTYt/B8XBfdjjEGW+fJX47AlYbo6xrQ2NTxHlLwkzYTxbtXO1BOFiQXVmvxKktPt8q7Im67pOyDDsV0l+TcCJF7qPs+VYepGCaok/4Kr73dezTUrz/SKj+GLY/LZKhIvsLHzzYcPJ3+7XhRBk5KC45uYeCw+12ORXqPSmUAjQzEtKTl3kvZGj7wSJViXWrBHRO34lCe47/y+V9tXf+Uczo48Bad6BO+i/59t4BmU3L3Z4QtlqP2qeCbL5evE/FY9vdC+NKJ10/5WbTrUy8EHY+UfAxLSSy1mgHWOUIIxBYPU6LedD15aucLVxa2NY4yf+DDamp0ByVSF3xmRc4482GfRri32h3G39oz8uYRoq/7oERxkTIbfrnH+Re1AFsgX7qwrEXlCHpLBN8Pz/L8vhmpoK56dNdJsSYQzJmzx3rnMtlRo1DEjc+wQbOx5ZsNyIEZixGuQIxQkSAKE8lv4H19uvF0cKQ9BypNbCZG2orFfQxO38JZBdsziQP5YWYyqjGaSYG9byhz19lJHe9nzFJaqOUWnYyUmh4KSyOEmQoTOp4z1vXiKPEIoQ7ThuqDd8QPgWe91ftKT/8VJCAdfxake3xAUR0ZifSOKHS1UsdsrBCRwOBtGRj2uTKq3PN1NqeUT8i3TC6+n7bVnvi3WAMBQHlZkUubql3tEHL9QztfsPWTyzp3KKvaHafz9ZtWnUo+1Yv9Np16NHcJaU596p32kWuS7Zj2emVOWnGYS2aMEnoud7XYhsmvqzNjeOc6UIn+lDutVFy3iqbbC/TyNgnmUqEL0wNqfZdhgEjvBVcfGvWjpBCzA== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR08MB5325.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(366004)(136003)(346002)(396003)(376002)(451199015)(316002)(38070700005)(6636002)(54906003)(38100700002)(99936003)(122000001)(84970400001)(55016003)(8936002)(6862004)(9686003)(186003)(7696005)(26005)(71200400001)(4326008)(52536014)(66476007)(66946007)(66556008)(76116006)(5660300002)(2906002)(30864003)(6506007)(86362001)(41300700001)(83380400001)(33656002)(8676002)(478600001)(64756008)(66446008);DIR:OUT;SFP:1101; Content-Type: multipart/mixed; boundary="_002_VI1PR08MB5325335D195073D1E5B2AB33FF009VI1PR08MB5325eurp_" MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9553 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 5023dbef-9c28-430d-7a8b-08dac3f2995d X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U3N2FnSWQEzEl8NRxRBU5vqQiIPRzwWFzRtWpgn7jqYxFsoYdU5aEFTFyS8pk3TPLf+I47hS1MOpLzu/BRXcSkM3jWjGkHNTBDHCr5+DGP8OOP35i5+dOq9jzwRbkG9IKGgJcDAKZYNDIrwyseMQtf8hf46UdHdPe6vXKZyOVxc9Ux9QAayxIEjKc5f+Ga3ddaiYnKUHJyuM/E05M+Z133mYHmO8JakaLCbQjg51mo4ePlY560Sf2mRRah3v+f5LkoE8YtCebsbdI995xxg5Qg6fi7PIAXPysO8MRmzV/AuVf9k3AmrCLhRq42taYdXvRQu9XvqN5oOU118Og1FGyNGrEsYrLGIZ/NMpn4iZ9Vi9RkJk7Xr4yoFR6OtJApiQNKRcbkh6BNl+cmGuFTh3Xh2x2DaJXLyiQBbbpJR9psR8x59qGg7CbU1eKAbG5IqUiw2BkHAOEq4pTPo34IpRnWj/H/sQxqxGI9SFkiGZP92xgdTeoU8PCpjSSdrmIUvMJkqtf1TZHuJU3iDQkXUUPtx1eaFRrrtQi/azGYINVdZAlIqbSckUeW8hIgcIpLKdi1zqypifxJ2yj1EFHj6Uzq2ryjj5YAY7WnNjX3ieikvGIb+gxwsPEkmcHubHbpJrrEp0C7SDDyJDkhe4P8N8wsbhd2fo6YM3EppzgPU40ID1ahzBmqBxyCCm75pbXCp2MkUxfO+ZtzXZIzT6ZyMfU3yciW0LaknkZt2qLOXcmh6IFS8QKGjN3POTtFZlKYTiAWp6/JE4NvPS0n7ziCrAbtZ1RxR3vAXwnsPdkY/sVqpPCEVsM0aFnSf0ERR3sj05IlBYSYAf4kpxz4mw6Prt4A== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199015)(36840700001)(46966006)(40470700004)(316002)(81166007)(6636002)(54906003)(356005)(82740400003)(99936003)(36860700001)(84970400001)(55016003)(8936002)(6862004)(40480700001)(9686003)(186003)(235185007)(336012)(7696005)(26005)(4326008)(82310400005)(52536014)(70206006)(70586007)(40460700003)(47076005)(5660300002)(2906002)(30864003)(6506007)(86362001)(41300700001)(83380400001)(33656002)(8676002)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 14:40:10.9031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25e9a035-017e-40bc-72cc-08dac3f2a2eb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8974 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SCC_5_SHORT_WORD_LINES,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_002_VI1PR08MB5325335D195073D1E5B2AB33FF009VI1PR08MB5325eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, > This name might cause confusion with the SVE iterators, where FULL means > "every bit of the register is used". How about something like VMOVE > instead? >=20 > With this change, I guess VALL_F16 represents "The set of all modes for > which the vld1 intrinsics are provided" and VMOVE or whatever is "All > Advanced SIMD modes suitable for moving, loading, and storing". > That is, VMOVE extends VALL_F16 with modes that are not manifested via > intrinsics. >=20 Done. > Where is the 2h used, and is it valid syntax in that context? >=20 > Same for later instances of 2h. They are, but they weren't meant to be in this patch. They belong in a sep= arate FP16 series that I won't get to finish for GCC 13 due not being able to finish writing all t= he tests. I have moved them to that patch series though. While the addp patch series has been killed, this patch is still good stand= alone and improves codegen as shown in the updated testcase. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_movv2hf): New. (mov, movmisalign, aarch64_dup_lane, aarch64_store_lane0, aarch64_simd_vec_set, @aarch64_simd_vec_copy_lane, vec_set, reduc__scal_, reduc__scal_, aarch64_reduc__internal, aarch64_get_lane, vec_init, vec_extract): Support V2HF. (aarch64_simd_dupv2hf): New. * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add E_V2HFmode. * config/aarch64/iterators.md (VHSDF_P): New. (V2F, VMOVE, nunits, Vtype, Vmtype, Vetype, stype, VEL, Vel, q, vp): Add V2HF. * config/arm/types.md (neon_fp_reduc_add_h): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/slp_1.c: Update testcase. --- inline copy of patch --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index f4152160084d6b6f34bd69f0ba6386c1ab50f77e..487a31010245accec28e779661e= 6c2d578fca4b7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -19,10 +19,10 @@ ;; . =20 (define_expand "mov" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VMOVE 0 "nonimmediate_operand") + (match_operand:VMOVE 1 "general_operand"))] "TARGET_SIMD" - " +{ /* Force the operand into a register if it is not an immediate whose use can be replaced with xzr. If the mode is 16 bytes wide, then we will be doing @@ -46,12 +46,11 @@ (define_expand "mov" aarch64_expand_vector_init (operands[0], operands[1]); DONE; } - " -) +}) =20 (define_expand "movmisalign" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VMOVE 0 "nonimmediate_operand") + (match_operand:VMOVE 1 "general_operand"))] "TARGET_SIMD && !STRICT_ALIGNMENT" { /* This pattern is not permitted to fail during expansion: if both argum= ents @@ -73,6 +72,16 @@ (define_insn "aarch64_simd_dup" [(set_attr "type" "neon_dup, neon_from_gp")] ) =20 +(define_insn "aarch64_simd_dupv2hf" + [(set (match_operand:V2HF 0 "register_operand" "=3Dw") + (vec_duplicate:V2HF + (match_operand:HF 1 "register_operand" "0")))] + "TARGET_SIMD" + "@ + sli\\t%d0, %d1, 16" + [(set_attr "type" "neon_shift_imm")] +) + (define_insn "aarch64_simd_dup" [(set (match_operand:VDQF_F16 0 "register_operand" "=3Dw,w") (vec_duplicate:VDQF_F16 @@ -85,10 +94,10 @@ (define_insn "aarch64_simd_dup" ) =20 (define_insn "aarch64_dup_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=3Dw") - (vec_duplicate:VALL_F16 + [(set (match_operand:VMOVE 0 "register_operand" "=3Dw") + (vec_duplicate:VMOVE (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w") + (match_operand:VMOVE 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" @@ -142,6 +151,29 @@ (define_insn "*aarch64_simd_mov" mov_reg, neon_move")] ) =20 +(define_insn "*aarch64_simd_movv2hf" + [(set (match_operand:V2HF 0 "nonimmediate_operand" + "=3Dw, m, m, w, ?r, ?w, ?r, w, w") + (match_operand:V2HF 1 "general_operand" + "m, Dz, w, w, w, r, r, Dz, Dn"))] + "TARGET_SIMD_F16INST + && (register_operand (operands[0], V2HFmode) + || aarch64_simd_reg_or_zero (operands[1], V2HFmode))" + "@ + ldr\\t%s0, %1 + str\\twzr, %0 + str\\t%s1, %0 + mov\\t%0.2s[0], %1.2s[0] + umov\\t%w0, %1.s[0] + fmov\\t%s0, %1 + mov\\t%0, %1 + movi\\t%d0, 0 + * return aarch64_output_simd_mov_immediate (operands[1], 32);" + [(set_attr "type" "neon_load1_1reg, store_8, neon_store1_1reg,\ + neon_logic, neon_to_gp, f_mcr,\ + mov_reg, neon_move, neon_move")] +) + (define_insn "*aarch64_simd_mov" [(set (match_operand:VQMOV 0 "nonimmediate_operand" "=3Dw, Umn, m, w, ?r, ?w, ?r, w") @@ -182,7 +214,7 @@ (define_insn "*aarch64_simd_mov" =20 (define_insn "aarch64_store_lane0" [(set (match_operand: 0 "memory_operand" "=3Dm") - (vec_select: (match_operand:VALL_F16 1 "register_operand" "w") + (vec_select: (match_operand:VMOVE 1 "register_operand" "w") (parallel [(match_operand 2 "const_int_operand" "n")])))] "TARGET_SIMD && ENDIAN_LANE_N (, INTVAL (operands[2])) =3D=3D 0" @@ -1035,11 +1067,11 @@ (define_insn "one_cmpl2" ) =20 (define_insn "aarch64_simd_vec_set" - [(set (match_operand:VALL_F16 0 "register_operand" "=3Dw,w,w") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VMOVE 0 "register_operand" "=3Dw,w,w") + (vec_merge:VMOVE + (vec_duplicate:VMOVE (match_operand: 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv")) - (match_operand:VALL_F16 3 "register_operand" "0,0,0") + (match_operand:VMOVE 3 "register_operand" "0,0,0") (match_operand:SI 2 "immediate_operand" "i,i,i")))] "TARGET_SIMD" { @@ -1061,14 +1093,14 @@ (define_insn "aarch64_simd_vec_set" ) =20 (define_insn "@aarch64_simd_vec_copy_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=3Dw") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VMOVE 0 "register_operand" "=3Dw") + (vec_merge:VMOVE + (vec_duplicate:VMOVE (vec_select: - (match_operand:VALL_F16 3 "register_operand" "w") + (match_operand:VMOVE 3 "register_operand" "w") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) - (match_operand:VALL_F16 1 "register_operand" "0") + (match_operand:VMOVE 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { @@ -1376,7 +1408,7 @@ (define_insn "vec_shr_" ) =20 (define_expand "vec_set" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VMOVE 0 "register_operand") (match_operand: 1 "aarch64_simd_nonimmediate_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" @@ -3495,7 +3527,7 @@ (define_insn "popcount2" ;; gimple_fold'd to the IFN_REDUC_(MAX|MIN) function. (This is FP smax/sm= in). (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINV)] "TARGET_SIMD" { @@ -3510,7 +3542,7 @@ (define_expand "reduc__scal_" =20 (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINNMV)] "TARGET_SIMD" { @@ -3554,8 +3586,8 @@ (define_insn "aarch64_reduc__internalv2si" ) =20 (define_insn "aarch64_reduc__internal" - [(set (match_operand:VHSDF 0 "register_operand" "=3Dw") - (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")] + [(set (match_operand:VHSDF_P 0 "register_operand" "=3Dw") + (unspec:VHSDF_P [(match_operand:VHSDF_P 1 "register_operand" "w")] FMAXMINV))] "TARGET_SIMD" "\\t%0, %1." @@ -4200,7 +4232,7 @@ (define_insn "*aarch64_get_lane_zero_extend= " (define_insn_and_split "aarch64_get_lane" [(set (match_operand: 0 "aarch64_simd_nonimmediate_operand" "=3D?r,= w, Utv") (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w, w, w") + (match_operand:VMOVE 1 "register_operand" "w, w, w") (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))] "TARGET_SIMD" { @@ -7981,7 +8013,7 @@ (define_expand "aarch64_st1" ;; Standard pattern name vec_init. =20 (define_expand "vec_init" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VMOVE 0 "register_operand") (match_operand 1 "" "")] "TARGET_SIMD" { @@ -8060,7 +8092,7 @@ (define_insn "aarch64_urecpe" =20 (define_expand "vec_extract" [(match_operand: 0 "aarch64_simd_nonimmediate_operand") - (match_operand:VALL_F16 1 "register_operand") + (match_operand:VMOVE 1 "register_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 84dbe2f4ea7d03b424602ed98a34e7824217dc91..35671cb86e374f9ded21d0e4944= c63bc2cbc0901 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3566,6 +3566,7 @@ aarch64_classify_vector_mode (machine_mode mode) case E_V8BFmode: case E_V4SFmode: case E_V2DFmode: + case E_V2HFmode: return TARGET_SIMD ? VEC_ADVSIMD : 0; =20 default: diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators= .md index 37d8161a33b1c399d80be82afa67613a087389d4..dfcf86a440e316c2abdbcc64636= 3d39e458d1a91 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -160,6 +160,10 @@ (define_mode_iterator VDQF [V2SF V4SF V2DF]) (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF]) +;; Advanced SIMD Float modes suitable for pairwise operations. +(define_mode_iterator VHSDF_P [(V4HF "TARGET_SIMD_F16INST") + (V8HF "TARGET_SIMD_F16INST") + V2SF V4SF V2DF (V2HF "TARGET_SIMD_F16INST")]) =20 ;; Advanced SIMD Float modes, and DF. (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) @@ -188,15 +192,23 @@ (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI = V2DF V2DI]) (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) =20 ;; Advanced SIMD Float modes with 2 elements. -(define_mode_iterator V2F [V2SF V2DF]) +(define_mode_iterator V2F [V2SF V2DF V2HF]) =20 ;; All Advanced SIMD modes on which we support any arithmetic operations. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF = V2DF]) =20 -;; All Advanced SIMD modes suitable for moving, loading, and storing. +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; except V2HF. (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) =20 +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; including V2HF +(define_mode_iterator VMOVE [V8QI V16QI V4HI V8HI V2SI V4SI V2DI + V4HF V8HF V4BF V8BF V2SF V4SF V2DF + (V2HF "TARGET_SIMD_F16INST")]) + + ;; The VALL_F16 modes except the 128-bit 2-element ones. (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF]) @@ -1076,7 +1088,7 @@ (define_mode_attr nunits [(V8QI "8") (V16QI "16") (V2SF "2") (V4SF "4") (V1DF "1") (V2DF "2") (DI "1") (DF "1") - (V8DI "8")]) + (V8DI "8") (V2HF "2")]) =20 ;; Map a mode to the number of bits in it, if the size of the mode ;; is constant. @@ -1090,6 +1102,7 @@ (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "= s") (DI "d")]) =20 ;; Give the length suffix letter for a sign- or zero-extension. (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) +(define_mode_attr sizel [(QI "b") (HI "h") (SI "")]) =20 ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) @@ -1193,7 +1206,7 @@ (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (V4HI "h") (V8HI "h") (V2SI "s") (V4SI "s") - (V2DI "d") + (V2DI "d") (V2HF "h") (V4HF "h") (V8HF "h") (V2SF "s") (V4SF "s") (V2DF "d") @@ -1285,7 +1298,7 @@ (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h")= (VNx4QI "w") (VNx2QI "d") ;; more accurately. (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") - (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") + (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") (V2HF "s") (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") (SI "s") (DI "d")]) =20 @@ -1360,8 +1373,8 @@ (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (V4HF "HF") (V8HF "HF") (V2SF "SF") (V4SF "SF") (DF "DF") (V2DF "DF") - (SI "SI") (HI "HI") - (QI "QI") + (SI "SI") (V2HF "HF") + (QI "QI") (HI "HI") (V4BF "BF") (V8BF "BF") (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI") (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI") @@ -1381,7 +1394,7 @@ (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (V2SF "sf") (V4SF "sf") (V2DF "df") (DF "df") (SI "si") (HI "hi") - (QI "qi") + (QI "qi") (V2HF "hf") (V4BF "bf") (V8BF "bf") (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") @@ -1866,7 +1879,7 @@ (define_mode_attr q [(V8QI "") (V16QI "_q") (V4HF "") (V8HF "_q") (V4BF "") (V8BF "_q") (V2SF "") (V4SF "_q") - (V2DF "_q") + (V2HF "") (V2DF "_q") (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "") (V2x8QI "") (V2x16QI "_q") (V2x4HI "") (V2x8HI "_q") @@ -1905,6 +1918,7 @@ (define_mode_attr vp [(V8QI "v") (V16QI "v") (V2SI "p") (V4SI "v") (V2DI "p") (V2DF "p") (V2SF "p") (V4SF "v") + (V2HF "p") (V4HF "v") (V8HF "v")]) =20 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 7d0504bdd944e9c0d1b545b0b66a9a1adc808714..3cfbc7a93cca1bea4925853e51d= 0a147c5722247 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -483,6 +483,7 @@ (define_attr "autodetect_type" ; neon_fp_minmax_s_q ; neon_fp_minmax_d ; neon_fp_minmax_d_q +; neon_fp_reduc_add_h ; neon_fp_reduc_add_s ; neon_fp_reduc_add_s_q ; neon_fp_reduc_add_d @@ -1033,6 +1034,7 @@ (define_attr "type" neon_fp_minmax_d,\ neon_fp_minmax_d_q,\ \ + neon_fp_reduc_add_h,\ neon_fp_reduc_add_s,\ neon_fp_reduc_add_s_q,\ neon_fp_reduc_add_d,\ @@ -1257,8 +1259,8 @@ (define_attr "is_neon_type" "yes,no" neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ - neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,= \ - neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, + neon_fp_reduc_add_h, neon_fp_reduc_add_s, neon_fp_reduc_add_s_q,= \ + neon_fp_reduc_add_d, neon_fp_reduc_add_d_q, neon_fp_reduc_minmax= _s,\ neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ neon_fp_reduc_minmax_d_q,\ neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/g= cc.target/aarch64/sve/slp_1.c index 07d71a63414b1066ea431e287286ad048515711a..e6021c5a42748701e5326a5c387= a39a0bbadc9e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c @@ -30,11 +30,9 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n)= \ TEST_ALL (VEC_PERM) =20 /* We should use one DUP for each of the 8-, 16- and 32-bit types, - although we currently use LD1RW for _Float16. We should use two - DUPs for each of the three 64-bit types. */ + We should use two DUPs for each of the three 64-bit types. */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, [hw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1rw\tz[0-9]+\.s, } 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 3 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, [dx]} 9 } } */ /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-= 9]+\.d\n} 3 } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ @@ -53,7 +51,7 @@ TEST_ALL (VEC_PERM) /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 6 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 6 } } */ /* { dg-final { scan-assembler-not {\tldr} } } */ -/* { dg-final { scan-assembler-times {\tstr} 2 } } */ -/* { dg-final { scan-assembler-times {\tstr\th[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {\tstr} } } */ +/* { dg-final { scan-assembler-not {\tstr\th[0-9]+} } } */ =20 /* { dg-final { scan-assembler-not {\tuqdec} } } */ --_002_VI1PR08MB5325335D195073D1E5B2AB33FF009VI1PR08MB5325eurp_ Content-Type: application/octet-stream; name="rb16244.patch" Content-Description: rb16244.patch Content-Disposition: attachment; filename="rb16244.patch"; size=15802; creation-date="Fri, 11 Nov 2022 14:39:40 GMT"; modification-date="Fri, 11 Nov 2022 14:39:54 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LXNpbWQubWQgYi9nY2MvY29u ZmlnL2FhcmNoNjQvYWFyY2g2NC1zaW1kLm1kCmluZGV4IGY0MTUyMTYwMDg0ZDZiNmYzNGJkNjlm MGJhNjM4NmMxYWI1MGY3N2UuLjQ4N2EzMTAxMDI0NWFjY2VjMjhlNzc5NjYxZTZjMmQ1NzhmY2E0 YjcgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LXNpbWQubWQKKysrIGIv Z2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQtc2ltZC5tZApAQCAtMTksMTAgKzE5LDEwIEBACiA7 OyA8aHR0cDovL3d3dy5nbnUub3JnL2xpY2Vuc2VzLz4uCiAKIChkZWZpbmVfZXhwYW5kICJtb3Y8 bW9kZT4iCi0gIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZBTExfRjE2IDAgIm5vbmltbWVkaWF0ZV9v cGVyYW5kIikKLQkobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAxICJnZW5lcmFsX29wZXJhbmQiKSld CisgIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZNT1ZFIDAgIm5vbmltbWVkaWF0ZV9vcGVyYW5kIikK KwkobWF0Y2hfb3BlcmFuZDpWTU9WRSAxICJnZW5lcmFsX29wZXJhbmQiKSldCiAgICJUQVJHRVRf U0lNRCIKLSAgIgorewogICAvKiBGb3JjZSB0aGUgb3BlcmFuZCBpbnRvIGEgcmVnaXN0ZXIgaWYg aXQgaXMgbm90IGFuCiAgICAgIGltbWVkaWF0ZSB3aG9zZSB1c2UgY2FuIGJlIHJlcGxhY2VkIHdp dGggeHpyLgogICAgICBJZiB0aGUgbW9kZSBpcyAxNiBieXRlcyB3aWRlLCB0aGVuIHdlIHdpbGwg YmUgZG9pbmcKQEAgLTQ2LDEyICs0NiwxMSBAQCAoZGVmaW5lX2V4cGFuZCAibW92PG1vZGU+Igog ICAgICAgYWFyY2g2NF9leHBhbmRfdmVjdG9yX2luaXQgKG9wZXJhbmRzWzBdLCBvcGVyYW5kc1sx XSk7CiAgICAgICBET05FOwogICAgIH0KLSAgIgotKQorfSkKIAogKGRlZmluZV9leHBhbmQgIm1v dm1pc2FsaWduPG1vZGU+IgotICBbKHNldCAobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAwICJub25p bW1lZGlhdGVfb3BlcmFuZCIpCi0gICAgICAgIChtYXRjaF9vcGVyYW5kOlZBTExfRjE2IDEgImdl bmVyYWxfb3BlcmFuZCIpKV0KKyAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6Vk1PVkUgMCAibm9uaW1t ZWRpYXRlX29wZXJhbmQiKQorICAgICAgICAobWF0Y2hfb3BlcmFuZDpWTU9WRSAxICJnZW5lcmFs X29wZXJhbmQiKSldCiAgICJUQVJHRVRfU0lNRCAmJiAhU1RSSUNUX0FMSUdOTUVOVCIKIHsKICAg LyogVGhpcyBwYXR0ZXJuIGlzIG5vdCBwZXJtaXR0ZWQgdG8gZmFpbCBkdXJpbmcgZXhwYW5zaW9u OiBpZiBib3RoIGFyZ3VtZW50cwpAQCAtNzMsNiArNzIsMTYgQEAgKGRlZmluZV9pbnNuICJhYXJj aDY0X3NpbWRfZHVwPG1vZGU+IgogICBbKHNldF9hdHRyICJ0eXBlIiAibmVvbl9kdXA8cT4sIG5l b25fZnJvbV9ncDxxPiIpXQogKQogCisoZGVmaW5lX2luc24gImFhcmNoNjRfc2ltZF9kdXB2Mmhm IgorICBbKHNldCAobWF0Y2hfb3BlcmFuZDpWMkhGIDAgInJlZ2lzdGVyX29wZXJhbmQiICI9dyIp CisJKHZlY19kdXBsaWNhdGU6VjJIRgorCSAgKG1hdGNoX29wZXJhbmQ6SEYgMSAicmVnaXN0ZXJf b3BlcmFuZCIgIjAiKSkpXQorICAiVEFSR0VUX1NJTUQiCisgICJACisgICBzbGlcXHQlZDAsICVk MSwgMTYiCisgIFsoc2V0X2F0dHIgInR5cGUiICJuZW9uX3NoaWZ0X2ltbSIpXQorKQorCiAoZGVm aW5lX2luc24gImFhcmNoNjRfc2ltZF9kdXA8bW9kZT4iCiAgIFsoc2V0IChtYXRjaF9vcGVyYW5k OlZEUUZfRjE2IDAgInJlZ2lzdGVyX29wZXJhbmQiICI9dyx3IikKIAkodmVjX2R1cGxpY2F0ZTpW RFFGX0YxNgpAQCAtODUsMTAgKzk0LDEwIEBAIChkZWZpbmVfaW5zbiAiYWFyY2g2NF9zaW1kX2R1 cDxtb2RlPiIKICkKIAogKGRlZmluZV9pbnNuICJhYXJjaDY0X2R1cF9sYW5lPG1vZGU+IgotICBb KHNldCAobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAwICJyZWdpc3Rlcl9vcGVyYW5kIiAiPXciKQot CSh2ZWNfZHVwbGljYXRlOlZBTExfRjE2CisgIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZNT1ZFIDAg InJlZ2lzdGVyX29wZXJhbmQiICI9dyIpCisJKHZlY19kdXBsaWNhdGU6Vk1PVkUKIAkgICh2ZWNf c2VsZWN0OjxWRUw+Ci0JICAgIChtYXRjaF9vcGVyYW5kOlZBTExfRjE2IDEgInJlZ2lzdGVyX29w ZXJhbmQiICJ3IikKKwkgICAgKG1hdGNoX29wZXJhbmQ6Vk1PVkUgMSAicmVnaXN0ZXJfb3BlcmFu ZCIgInciKQogCSAgICAocGFyYWxsZWwgWyhtYXRjaF9vcGVyYW5kOlNJIDIgImltbWVkaWF0ZV9v cGVyYW5kIiAiaSIpXSkKICAgICAgICAgICApKSldCiAgICJUQVJHRVRfU0lNRCIKQEAgLTE0Miw2 ICsxNTEsMjkgQEAgKGRlZmluZV9pbnNuICIqYWFyY2g2NF9zaW1kX21vdjxWRE1PVjptb2RlPiIK IAkJICAgICBtb3ZfcmVnLCBuZW9uX21vdmU8cT4iKV0KICkKIAorKGRlZmluZV9pbnNuICIqYWFy Y2g2NF9zaW1kX21vdnYyaGYiCisgIFsoc2V0IChtYXRjaF9vcGVyYW5kOlYySEYgMCAibm9uaW1t ZWRpYXRlX29wZXJhbmQiCisJCSI9dywgbSwgIG0sICB3LCA/ciwgP3csID9yLCB3LCB3IikKKwko bWF0Y2hfb3BlcmFuZDpWMkhGIDEgImdlbmVyYWxfb3BlcmFuZCIKKwkJIm0sICBEeiwgdywgIHcs ICB3LCAgciwgIHIsIER6LCBEbiIpKV0KKyAgIlRBUkdFVF9TSU1EX0YxNklOU1QKKyAgICYmIChy ZWdpc3Rlcl9vcGVyYW5kIChvcGVyYW5kc1swXSwgVjJIRm1vZGUpCisgICAgICAgfHwgYWFyY2g2 NF9zaW1kX3JlZ19vcl96ZXJvIChvcGVyYW5kc1sxXSwgVjJIRm1vZGUpKSIKKyAgICJACisgICAg bGRyXFx0JXMwLCAlMQorICAgIHN0clxcdHd6ciwgJTAKKyAgICBzdHJcXHQlczEsICUwCisgICAg bW92XFx0JTAuMnNbMF0sICUxLjJzWzBdCisgICAgdW1vdlxcdCV3MCwgJTEuc1swXQorICAgIGZt b3ZcXHQlczAsICUxCisgICAgbW92XFx0JTAsICUxCisgICAgbW92aVxcdCVkMCwgMAorICAgICog cmV0dXJuIGFhcmNoNjRfb3V0cHV0X3NpbWRfbW92X2ltbWVkaWF0ZSAob3BlcmFuZHNbMV0sIDMy KTsiCisgIFsoc2V0X2F0dHIgInR5cGUiICJuZW9uX2xvYWQxXzFyZWcsIHN0b3JlXzgsIG5lb25f c3RvcmUxXzFyZWcsXAorCQkgICAgIG5lb25fbG9naWMsIG5lb25fdG9fZ3AsIGZfbWNyLFwKKwkJ ICAgICBtb3ZfcmVnLCBuZW9uX21vdmUsIG5lb25fbW92ZSIpXQorKQorCiAoZGVmaW5lX2luc24g IiphYXJjaDY0X3NpbWRfbW92PFZRTU9WOm1vZGU+IgogICBbKHNldCAobWF0Y2hfb3BlcmFuZDpW UU1PViAwICJub25pbW1lZGlhdGVfb3BlcmFuZCIKIAkJIj13LCBVbW4sICBtLCAgdywgP3IsID93 LCA/ciwgdyIpCkBAIC0xODIsNyArMjE0LDcgQEAgKGRlZmluZV9pbnNuICIqYWFyY2g2NF9zaW1k X21vdjxWUU1PVjptb2RlPiIKIAogKGRlZmluZV9pbnNuICJhYXJjaDY0X3N0b3JlX2xhbmUwPG1v ZGU+IgogICBbKHNldCAobWF0Y2hfb3BlcmFuZDo8VkVMPiAwICJtZW1vcnlfb3BlcmFuZCIgIj1t IikKLQkodmVjX3NlbGVjdDo8VkVMPiAobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAxICJyZWdpc3Rl cl9vcGVyYW5kIiAidyIpCisJKHZlY19zZWxlY3Q6PFZFTD4gKG1hdGNoX29wZXJhbmQ6Vk1PVkUg MSAicmVnaXN0ZXJfb3BlcmFuZCIgInciKQogCQkJKHBhcmFsbGVsIFsobWF0Y2hfb3BlcmFuZCAy ICJjb25zdF9pbnRfb3BlcmFuZCIgIm4iKV0pKSldCiAgICJUQVJHRVRfU0lNRAogICAgJiYgRU5E SUFOX0xBTkVfTiAoPG51bml0cz4sIElOVFZBTCAob3BlcmFuZHNbMl0pKSA9PSAwIgpAQCAtMTAz NSwxMSArMTA2NywxMSBAQCAoZGVmaW5lX2luc24gIm9uZV9jbXBsPG1vZGU+MiIKICkKIAogKGRl ZmluZV9pbnNuICJhYXJjaDY0X3NpbWRfdmVjX3NldDxtb2RlPiIKLSAgWyhzZXQgKG1hdGNoX29w ZXJhbmQ6VkFMTF9GMTYgMCAicmVnaXN0ZXJfb3BlcmFuZCIgIj13LHcsdyIpCi0JKHZlY19tZXJn ZTpWQUxMX0YxNgotCSAgICAodmVjX2R1cGxpY2F0ZTpWQUxMX0YxNgorICBbKHNldCAobWF0Y2hf b3BlcmFuZDpWTU9WRSAwICJyZWdpc3Rlcl9vcGVyYW5kIiAiPXcsdyx3IikKKwkodmVjX21lcmdl OlZNT1ZFCisJICAgICh2ZWNfZHVwbGljYXRlOlZNT1ZFCiAJCShtYXRjaF9vcGVyYW5kOjxWRUw+ IDEgImFhcmNoNjRfc2ltZF9ub25pbW1lZGlhdGVfb3BlcmFuZCIgIncsP3IsVXR2IikpCi0JICAg IChtYXRjaF9vcGVyYW5kOlZBTExfRjE2IDMgInJlZ2lzdGVyX29wZXJhbmQiICIwLDAsMCIpCisJ ICAgIChtYXRjaF9vcGVyYW5kOlZNT1ZFIDMgInJlZ2lzdGVyX29wZXJhbmQiICIwLDAsMCIpCiAJ ICAgIChtYXRjaF9vcGVyYW5kOlNJIDIgImltbWVkaWF0ZV9vcGVyYW5kIiAiaSxpLGkiKSkpXQog ICAiVEFSR0VUX1NJTUQiCiAgIHsKQEAgLTEwNjEsMTQgKzEwOTMsMTQgQEAgKGRlZmluZV9pbnNu ICJhYXJjaDY0X3NpbWRfdmVjX3NldDxtb2RlPiIKICkKIAogKGRlZmluZV9pbnNuICJAYWFyY2g2 NF9zaW1kX3ZlY19jb3B5X2xhbmU8bW9kZT4iCi0gIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZBTExf RjE2IDAgInJlZ2lzdGVyX29wZXJhbmQiICI9dyIpCi0JKHZlY19tZXJnZTpWQUxMX0YxNgotCSAg ICAodmVjX2R1cGxpY2F0ZTpWQUxMX0YxNgorICBbKHNldCAobWF0Y2hfb3BlcmFuZDpWTU9WRSAw ICJyZWdpc3Rlcl9vcGVyYW5kIiAiPXciKQorCSh2ZWNfbWVyZ2U6Vk1PVkUKKwkgICAgKHZlY19k dXBsaWNhdGU6Vk1PVkUKIAkgICAgICAodmVjX3NlbGVjdDo8VkVMPgotCQkobWF0Y2hfb3BlcmFu ZDpWQUxMX0YxNiAzICJyZWdpc3Rlcl9vcGVyYW5kIiAidyIpCisJCShtYXRjaF9vcGVyYW5kOlZN T1ZFIDMgInJlZ2lzdGVyX29wZXJhbmQiICJ3IikKIAkJKHBhcmFsbGVsCiAJCSAgWyhtYXRjaF9v cGVyYW5kOlNJIDQgImltbWVkaWF0ZV9vcGVyYW5kIiAiaSIpXSkpKQotCSAgICAobWF0Y2hfb3Bl cmFuZDpWQUxMX0YxNiAxICJyZWdpc3Rlcl9vcGVyYW5kIiAiMCIpCisJICAgIChtYXRjaF9vcGVy YW5kOlZNT1ZFIDEgInJlZ2lzdGVyX29wZXJhbmQiICIwIikKIAkgICAgKG1hdGNoX29wZXJhbmQ6 U0kgMiAiaW1tZWRpYXRlX29wZXJhbmQiICJpIikpKV0KICAgIlRBUkdFVF9TSU1EIgogICB7CkBA IC0xMzc2LDcgKzE0MDgsNyBAQCAoZGVmaW5lX2luc24gInZlY19zaHJfPG1vZGU+IgogKQogCiAo ZGVmaW5lX2V4cGFuZCAidmVjX3NldDxtb2RlPiIKLSAgWyhtYXRjaF9vcGVyYW5kOlZBTExfRjE2 IDAgInJlZ2lzdGVyX29wZXJhbmQiKQorICBbKG1hdGNoX29wZXJhbmQ6Vk1PVkUgMCAicmVnaXN0 ZXJfb3BlcmFuZCIpCiAgICAobWF0Y2hfb3BlcmFuZDo8VkVMPiAxICJhYXJjaDY0X3NpbWRfbm9u aW1tZWRpYXRlX29wZXJhbmQiKQogICAgKG1hdGNoX29wZXJhbmQ6U0kgMiAiaW1tZWRpYXRlX29w ZXJhbmQiKV0KICAgIlRBUkdFVF9TSU1EIgpAQCAtMzQ5NSw3ICszNTI3LDcgQEAgKGRlZmluZV9p bnNuICJwb3Bjb3VudDxtb2RlPjIiCiA7OyBnaW1wbGVfZm9sZCdkIHRvIHRoZSBJRk5fUkVEVUNf KE1BWHxNSU4pIGZ1bmN0aW9uLiAgKFRoaXMgaXMgRlAgc21heC9zbWluKS4KIChkZWZpbmVfZXhw YW5kICJyZWR1Y188b3B0YWI+X3NjYWxfPG1vZGU+IgogICBbKG1hdGNoX29wZXJhbmQ6PFZFTD4g MCAicmVnaXN0ZXJfb3BlcmFuZCIpCi0gICAodW5zcGVjOjxWRUw+IFsobWF0Y2hfb3BlcmFuZDpW SFNERiAxICJyZWdpc3Rlcl9vcGVyYW5kIildCisgICAodW5zcGVjOjxWRUw+IFsobWF0Y2hfb3Bl cmFuZDpWSFNERl9QIDEgInJlZ2lzdGVyX29wZXJhbmQiKV0KIAkJIEZNQVhNSU5WKV0KICAgIlRB UkdFVF9TSU1EIgogICB7CkBAIC0zNTEwLDcgKzM1NDIsNyBAQCAoZGVmaW5lX2V4cGFuZCAicmVk dWNfPG9wdGFiPl9zY2FsXzxtb2RlPiIKIAogKGRlZmluZV9leHBhbmQgInJlZHVjXzxmbWF4bWlu Pl9zY2FsXzxtb2RlPiIKICAgWyhtYXRjaF9vcGVyYW5kOjxWRUw+IDAgInJlZ2lzdGVyX29wZXJh bmQiKQotICAgKHVuc3BlYzo8VkVMPiBbKG1hdGNoX29wZXJhbmQ6VkhTREYgMSAicmVnaXN0ZXJf b3BlcmFuZCIpXQorICAgKHVuc3BlYzo8VkVMPiBbKG1hdGNoX29wZXJhbmQ6VkhTREZfUCAxICJy ZWdpc3Rlcl9vcGVyYW5kIildCiAJCSBGTUFYTUlOTk1WKV0KICAgIlRBUkdFVF9TSU1EIgogICB7 CkBAIC0zNTU0LDggKzM1ODYsOCBAQCAoZGVmaW5lX2luc24gImFhcmNoNjRfcmVkdWNfPG9wdGFi Pl9pbnRlcm5hbHYyc2kiCiApCiAKIChkZWZpbmVfaW5zbiAiYWFyY2g2NF9yZWR1Y188b3B0YWI+ X2ludGVybmFsPG1vZGU+IgotIFsoc2V0IChtYXRjaF9vcGVyYW5kOlZIU0RGIDAgInJlZ2lzdGVy X29wZXJhbmQiICI9dyIpCi0gICAgICAgKHVuc3BlYzpWSFNERiBbKG1hdGNoX29wZXJhbmQ6VkhT REYgMSAicmVnaXN0ZXJfb3BlcmFuZCIgInciKV0KKyBbKHNldCAobWF0Y2hfb3BlcmFuZDpWSFNE Rl9QIDAgInJlZ2lzdGVyX29wZXJhbmQiICI9dyIpCisgICAgICAgKHVuc3BlYzpWSFNERl9QIFso bWF0Y2hfb3BlcmFuZDpWSFNERl9QIDEgInJlZ2lzdGVyX29wZXJhbmQiICJ3IildCiAJCSAgICAg IEZNQVhNSU5WKSldCiAgIlRBUkdFVF9TSU1EIgogICI8bWF4bWluX3Vuc19vcD48dnA+XFx0JTxW ZXR5cGU+MCwgJTEuPFZ0eXBlPiIKQEAgLTQyMDAsNyArNDIzMiw3IEBAIChkZWZpbmVfaW5zbiAi KmFhcmNoNjRfZ2V0X2xhbmVfemVyb19leHRlbmQ8R1BJOm1vZGU+PFZEUVFIOm1vZGU+IgogKGRl ZmluZV9pbnNuX2FuZF9zcGxpdCAiYWFyY2g2NF9nZXRfbGFuZTxtb2RlPiIKICAgWyhzZXQgKG1h dGNoX29wZXJhbmQ6PFZFTD4gMCAiYWFyY2g2NF9zaW1kX25vbmltbWVkaWF0ZV9vcGVyYW5kIiAi PT9yLCB3LCBVdHYiKQogCSh2ZWNfc2VsZWN0OjxWRUw+Ci0JICAobWF0Y2hfb3BlcmFuZDpWQUxM X0YxNiAxICJyZWdpc3Rlcl9vcGVyYW5kIiAidywgdywgdyIpCisJICAobWF0Y2hfb3BlcmFuZDpW TU9WRSAxICJyZWdpc3Rlcl9vcGVyYW5kIiAidywgdywgdyIpCiAJICAocGFyYWxsZWwgWyhtYXRj aF9vcGVyYW5kOlNJIDIgImltbWVkaWF0ZV9vcGVyYW5kIiAiaSwgaSwgaSIpXSkpKV0KICAgIlRB UkdFVF9TSU1EIgogICB7CkBAIC03OTgxLDcgKzgwMTMsNyBAQCAoZGVmaW5lX2V4cGFuZCAiYWFy Y2g2NF9zdDE8VkFMTF9GMTY6bW9kZT4iCiA7OyBTdGFuZGFyZCBwYXR0ZXJuIG5hbWUgdmVjX2lu aXQ8bW9kZT48VmVsPi4KIAogKGRlZmluZV9leHBhbmQgInZlY19pbml0PG1vZGU+PFZlbD4iCi0g IFsobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAwICJyZWdpc3Rlcl9vcGVyYW5kIikKKyAgWyhtYXRj aF9vcGVyYW5kOlZNT1ZFIDAgInJlZ2lzdGVyX29wZXJhbmQiKQogICAgKG1hdGNoX29wZXJhbmQg MSAiIiAiIildCiAgICJUQVJHRVRfU0lNRCIKIHsKQEAgLTgwNjAsNyArODA5Miw3IEBAIChkZWZp bmVfaW5zbiAiYWFyY2g2NF91cmVjcGU8bW9kZT4iCiAKIChkZWZpbmVfZXhwYW5kICJ2ZWNfZXh0 cmFjdDxtb2RlPjxWZWw+IgogICBbKG1hdGNoX29wZXJhbmQ6PFZFTD4gMCAiYWFyY2g2NF9zaW1k X25vbmltbWVkaWF0ZV9vcGVyYW5kIikKLSAgIChtYXRjaF9vcGVyYW5kOlZBTExfRjE2IDEgInJl Z2lzdGVyX29wZXJhbmQiKQorICAgKG1hdGNoX29wZXJhbmQ6Vk1PVkUgMSAicmVnaXN0ZXJfb3Bl cmFuZCIpCiAgICAobWF0Y2hfb3BlcmFuZDpTSSAyICJpbW1lZGlhdGVfb3BlcmFuZCIpXQogICAi VEFSR0VUX1NJTUQiCiB7CmRpZmYgLS1naXQgYS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC5j YyBiL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmNjCmluZGV4IDg0ZGJlMmY0ZWE3ZDAzYjQy NDYwMmVkOThhMzRlNzgyNDIxN2RjOTEuLjM1NjcxY2I4NmUzNzRmOWRlZDIxZDBlNDk0NGM2M2Jj MmNiYzA5MDEgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmNjCisrKyBi L2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmNjCkBAIC0zNTY2LDYgKzM1NjYsNyBAQCBhYXJj aDY0X2NsYXNzaWZ5X3ZlY3Rvcl9tb2RlIChtYWNoaW5lX21vZGUgbW9kZSkKICAgICBjYXNlIEVf VjhCRm1vZGU6CiAgICAgY2FzZSBFX1Y0U0Ztb2RlOgogICAgIGNhc2UgRV9WMkRGbW9kZToKKyAg ICBjYXNlIEVfVjJIRm1vZGU6CiAgICAgICByZXR1cm4gVEFSR0VUX1NJTUQgPyBWRUNfQURWU0lN RCA6IDA7CiAKICAgICBkZWZhdWx0OgpkaWZmIC0tZ2l0IGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2l0 ZXJhdG9ycy5tZCBiL2djYy9jb25maWcvYWFyY2g2NC9pdGVyYXRvcnMubWQKaW5kZXggMzdkODE2 MWEzM2IxYzM5OWQ4MGJlODJhZmE2NzYxM2EwODczODlkNC4uZGZjZjg2YTQ0MGUzMTZjMmFiZGJj YzY0NjM2M2QzOWU0NThkMWE5MSAxMDA2NDQKLS0tIGEvZ2NjL2NvbmZpZy9hYXJjaDY0L2l0ZXJh dG9ycy5tZAorKysgYi9nY2MvY29uZmlnL2FhcmNoNjQvaXRlcmF0b3JzLm1kCkBAIC0xNjAsNiAr MTYwLDEwIEBAIChkZWZpbmVfbW9kZV9pdGVyYXRvciBWRFFGIFtWMlNGIFY0U0YgVjJERl0pCiAo ZGVmaW5lX21vZGVfaXRlcmF0b3IgVkhTREYgWyhWNEhGICJUQVJHRVRfU0lNRF9GMTZJTlNUIikK IAkJCSAgICAgKFY4SEYgIlRBUkdFVF9TSU1EX0YxNklOU1QiKQogCQkJICAgICBWMlNGIFY0U0Yg VjJERl0pCis7OyBBZHZhbmNlZCBTSU1EIEZsb2F0IG1vZGVzIHN1aXRhYmxlIGZvciBwYWlyd2lz ZSBvcGVyYXRpb25zLgorKGRlZmluZV9tb2RlX2l0ZXJhdG9yIFZIU0RGX1AgWyhWNEhGICJUQVJH RVRfU0lNRF9GMTZJTlNUIikKKwkJCSAgICAgICAoVjhIRiAiVEFSR0VUX1NJTURfRjE2SU5TVCIp CisJCQkgICAgICAgVjJTRiBWNFNGIFYyREYgKFYySEYgIlRBUkdFVF9TSU1EX0YxNklOU1QiKV0p CiAKIDs7IEFkdmFuY2VkIFNJTUQgRmxvYXQgbW9kZXMsIGFuZCBERi4KIChkZWZpbmVfbW9kZV9p dGVyYXRvciBWRFFGX0RGIFtWMlNGIFY0U0YgVjJERiBERl0pCkBAIC0xODgsMTUgKzE5MiwyMyBA QCAoZGVmaW5lX21vZGVfaXRlcmF0b3IgVkRRRl9DT05EIFtWMlNGIFYyU0kgVjRTRiBWNFNJIFYy REYgVjJESV0pCiAoZGVmaW5lX21vZGVfaXRlcmF0b3IgVkFMTEYgW1YyU0YgVjRTRiBWMkRGIFNG IERGXSkKIAogOzsgQWR2YW5jZWQgU0lNRCBGbG9hdCBtb2RlcyB3aXRoIDIgZWxlbWVudHMuCi0o ZGVmaW5lX21vZGVfaXRlcmF0b3IgVjJGIFtWMlNGIFYyREZdKQorKGRlZmluZV9tb2RlX2l0ZXJh dG9yIFYyRiBbVjJTRiBWMkRGIFYySEZdKQogCiA7OyBBbGwgQWR2YW5jZWQgU0lNRCBtb2RlcyBv biB3aGljaCB3ZSBzdXBwb3J0IGFueSBhcml0aG1ldGljIG9wZXJhdGlvbnMuCiAoZGVmaW5lX21v ZGVfaXRlcmF0b3IgVkFMTCBbVjhRSSBWMTZRSSBWNEhJIFY4SEkgVjJTSSBWNFNJIFYyREkgVjJT RiBWNFNGIFYyREZdKQogCi07OyBBbGwgQWR2YW5jZWQgU0lNRCBtb2RlcyBzdWl0YWJsZSBmb3Ig bW92aW5nLCBsb2FkaW5nLCBhbmQgc3RvcmluZy4KKzs7IEFsbCBBZHZhbmNlZCBTSU1EIG1vZGVz IHN1aXRhYmxlIGZvciBtb3ZpbmcsIGxvYWRpbmcsIGFuZCBzdG9yaW5nCis7OyBleGNlcHQgVjJI Ri4KIChkZWZpbmVfbW9kZV9pdGVyYXRvciBWQUxMX0YxNiBbVjhRSSBWMTZRSSBWNEhJIFY4SEkg VjJTSSBWNFNJIFYyREkKIAkJCQlWNEhGIFY4SEYgVjRCRiBWOEJGIFYyU0YgVjRTRiBWMkRGXSkK IAorOzsgQWxsIEFkdmFuY2VkIFNJTUQgbW9kZXMgc3VpdGFibGUgZm9yIG1vdmluZywgbG9hZGlu ZywgYW5kIHN0b3JpbmcKKzs7IGluY2x1ZGluZyBWMkhGCisoZGVmaW5lX21vZGVfaXRlcmF0b3Ig Vk1PVkUgW1Y4UUkgVjE2UUkgVjRISSBWOEhJIFYyU0kgVjRTSSBWMkRJCisJCQkgICAgIFY0SEYg VjhIRiBWNEJGIFY4QkYgVjJTRiBWNFNGIFYyREYKKwkJCSAgICAgKFYySEYgIlRBUkdFVF9TSU1E X0YxNklOU1QiKV0pCisKKwogOzsgVGhlIFZBTExfRjE2IG1vZGVzIGV4Y2VwdCB0aGUgMTI4LWJp dCAyLWVsZW1lbnQgb25lcy4KIChkZWZpbmVfbW9kZV9pdGVyYXRvciBWQUxMX0YxNl9OT19WMlEg W1Y4UUkgVjE2UUkgVjRISSBWOEhJIFYyU0kgVjRTSQogCQkJCVY0SEYgVjhIRiBWMlNGIFY0U0Zd KQpAQCAtMTA3Niw3ICsxMDg4LDcgQEAgKGRlZmluZV9tb2RlX2F0dHIgbnVuaXRzIFsoVjhRSSAi OCIpIChWMTZRSSAiMTYiKQogCQkJICAoVjJTRiAiMiIpIChWNFNGICI0IikKIAkJCSAgKFYxREYg IjEiKSAoVjJERiAiMiIpCiAJCQkgIChESSAiMSIpIChERiAiMSIpCi0JCQkgIChWOERJICI4Iild KQorCQkJICAoVjhESSAiOCIpIChWMkhGICIyIildKQogCiA7OyBNYXAgYSBtb2RlIHRvIHRoZSBu dW1iZXIgb2YgYml0cyBpbiBpdCwgaWYgdGhlIHNpemUgb2YgdGhlIG1vZGUKIDs7IGlzIGNvbnN0 YW50LgpAQCAtMTA5MCw2ICsxMTAyLDcgQEAgKGRlZmluZV9tb2RlX2F0dHIgcyBbKEhGICJoIikg KFNGICJzIikgKERGICJkIikgKFNJICJzIikgKERJICJkIildKQogCiA7OyBHaXZlIHRoZSBsZW5n dGggc3VmZml4IGxldHRlciBmb3IgYSBzaWduLSBvciB6ZXJvLWV4dGVuc2lvbi4KIChkZWZpbmVf bW9kZV9hdHRyIHNpemUgWyhRSSAiYiIpIChISSAiaCIpIChTSSAidyIpXSkKKyhkZWZpbmVfbW9k ZV9hdHRyIHNpemVsIFsoUUkgImIiKSAoSEkgImgiKSAoU0kgIiIpXSkKIAogOzsgR2l2ZSB0aGUg bnVtYmVyIG9mIGJpdHMgaW4gdGhlIG1vZGUKIChkZWZpbmVfbW9kZV9hdHRyIHNpemVuIFsoUUkg IjgiKSAoSEkgIjE2IikgKFNJICIzMiIpIChESSAiNjQiKV0pCkBAIC0xMTkzLDcgKzEyMDYsNyBA QCAoZGVmaW5lX21vZGVfYXR0ciBWbW50eXBlIFsoVjhISSAiLjhiIikgKFY0U0kgIi40aCIpCiAo ZGVmaW5lX21vZGVfYXR0ciBWZXR5cGUgWyhWOFFJICJiIikgKFYxNlFJICJiIikKIAkJCSAgKFY0 SEkgImgiKSAoVjhISSAgImgiKQogCQkJICAoVjJTSSAicyIpIChWNFNJICAicyIpCi0JCQkgIChW MkRJICJkIikKKwkJCSAgKFYyREkgImQiKSAoVjJIRiAgImgiKQogCQkJICAoVjRIRiAiaCIpIChW OEhGICAiaCIpCiAJCQkgIChWMlNGICJzIikgKFY0U0YgICJzIikKIAkJCSAgKFYyREYgImQiKQpA QCAtMTI4NSw3ICsxMjk4LDcgQEAgKGRlZmluZV9tb2RlX2F0dHIgVmN3dHlwZSBbKFZOeDE2UUkg ImIiKSAoVk54OFFJICJoIikgKFZOeDRRSSAidyIpIChWTngyUUkgImQiKQogOzsgbW9yZSBhY2N1 cmF0ZWx5LgogKGRlZmluZV9tb2RlX2F0dHIgc3R5cGUgWyhWOFFJICJiIikgKFYxNlFJICJiIikg KFY0SEkgInMiKSAoVjhISSAicyIpCiAJCQkgKFYyU0kgInMiKSAoVjRTSSAicyIpIChWMkRJICJk IikgKFY0SEYgInMiKQotCQkJIChWOEhGICJzIikgKFYyU0YgInMiKSAoVjRTRiAicyIpIChWMkRG ICJkIikKKwkJCSAoVjhIRiAicyIpIChWMlNGICJzIikgKFY0U0YgInMiKSAoVjJERiAiZCIpIChW MkhGICJzIikKIAkJCSAoSEYgInMiKSAoU0YgInMiKSAoREYgImQiKSAoUUkgImIiKSAoSEkgInMi KQogCQkJIChTSSAicyIpIChESSAiZCIpXSkKIApAQCAtMTM2MCw4ICsxMzczLDggQEAgKGRlZmlu ZV9tb2RlX2F0dHIgVkVMIFsoVjhRSSAgIlFJIikgKFYxNlFJICJRSSIpCiAJCSAgICAgICAoVjRI RiAiSEYiKSAoVjhIRiAgIkhGIikKIAkJICAgICAgIChWMlNGICJTRiIpIChWNFNGICAiU0YiKQog CQkgICAgICAgKERGICAgIkRGIikgKFYyREYgICJERiIpCi0JCSAgICAgICAoU0kgICAiU0kiKSAo SEkgICAgIkhJIikKLQkJICAgICAgIChRSSAgICJRSSIpCisJCSAgICAgICAoU0kgICAiU0kiKSAo VjJIRiAgIkhGIikKKwkJICAgICAgIChRSSAgICJRSSIpIChISSAgICAiSEkiKQogCQkgICAgICAg KFY0QkYgIkJGIikgKFY4QkYgIkJGIikKIAkJICAgICAgIChWTngxNlFJICJRSSIpIChWTng4UUkg IlFJIikgKFZOeDRRSSAiUUkiKSAoVk54MlFJICJRSSIpCiAJCSAgICAgICAoVk54OEhJICJISSIp IChWTng0SEkgIkhJIikgKFZOeDJISSAiSEkiKQpAQCAtMTM4MSw3ICsxMzk0LDcgQEAgKGRlZmlu ZV9tb2RlX2F0dHIgVmVsIFsoVjhRSSAicWkiKSAoVjE2UUkgInFpIikKIAkJICAgICAgIChWMlNG ICJzZiIpIChWNFNGICJzZiIpCiAJCSAgICAgICAoVjJERiAiZGYiKSAoREYgICAiZGYiKQogCQkg ICAgICAgKFNJICAgInNpIikgKEhJICAgImhpIikKLQkJICAgICAgIChRSSAgICJxaSIpCisJCSAg ICAgICAoUUkgICAicWkiKSAoVjJIRiAiaGYiKQogCQkgICAgICAgKFY0QkYgImJmIikgKFY4QkYg ImJmIikKIAkJICAgICAgIChWTngxNlFJICJxaSIpIChWTng4UUkgInFpIikgKFZOeDRRSSAicWki KSAoVk54MlFJICJxaSIpCiAJCSAgICAgICAoVk54OEhJICJoaSIpIChWTng0SEkgImhpIikgKFZO eDJISSAiaGkiKQpAQCAtMTg2Niw3ICsxODc5LDcgQEAgKGRlZmluZV9tb2RlX2F0dHIgcSBbKFY4 UUkgIiIpIChWMTZRSSAiX3EiKQogCQkgICAgIChWNEhGICIiKSAoVjhIRiAiX3EiKQogCQkgICAg IChWNEJGICIiKSAoVjhCRiAiX3EiKQogCQkgICAgIChWMlNGICIiKSAoVjRTRiAgIl9xIikKLQkJ CSAgICAgICAoVjJERiAgIl9xIikKKwkJICAgICAoVjJIRiAiIikgKFYyREYgICJfcSIpCiAJCSAg ICAgKFFJICIiKSAoSEkgIiIpIChTSSAiIikgKERJICIiKSAoSEYgIiIpIChTRiAiIikgKERGICIi KQogCQkgICAgIChWMng4UUkgIiIpIChWMngxNlFJICJfcSIpCiAJCSAgICAgKFYyeDRISSAiIikg KFYyeDhISSAiX3EiKQpAQCAtMTkwNSw2ICsxOTE4LDcgQEAgKGRlZmluZV9tb2RlX2F0dHIgdnAg WyhWOFFJICJ2IikgKFYxNlFJICJ2IikKIAkJICAgICAgKFYyU0kgInAiKSAoVjRTSSAgInYiKQog CQkgICAgICAoVjJESSAicCIpIChWMkRGICAicCIpCiAJCSAgICAgIChWMlNGICJwIikgKFY0U0Yg ICJ2IikKKwkJICAgICAgKFYySEYgInAiKQogCQkgICAgICAoVjRIRiAidiIpIChWOEhGICAidiIp XSkKIAogKGRlZmluZV9tb2RlX2F0dHIgdnNpMnFpIFsoVjJTSSAidjhxaSIpIChWNFNJICJ2MTZx aSIpCmRpZmYgLS1naXQgYS9nY2MvY29uZmlnL2FybS90eXBlcy5tZCBiL2djYy9jb25maWcvYXJt L3R5cGVzLm1kCmluZGV4IDdkMDUwNGJkZDk0NGU5YzBkMWI1NDViMGI2NmE5YTFhZGM4MDg3MTQu LjNjZmJjN2E5M2NjYTFiZWE0OTI1ODUzZTUxZDBhMTQ3YzU3MjIyNDcgMTAwNjQ0Ci0tLSBhL2dj Yy9jb25maWcvYXJtL3R5cGVzLm1kCisrKyBiL2djYy9jb25maWcvYXJtL3R5cGVzLm1kCkBAIC00 ODMsNiArNDgzLDcgQEAgKGRlZmluZV9hdHRyICJhdXRvZGV0ZWN0X3R5cGUiCiA7IG5lb25fZnBf bWlubWF4X3NfcQogOyBuZW9uX2ZwX21pbm1heF9kCiA7IG5lb25fZnBfbWlubWF4X2RfcQorOyBu ZW9uX2ZwX3JlZHVjX2FkZF9oCiA7IG5lb25fZnBfcmVkdWNfYWRkX3MKIDsgbmVvbl9mcF9yZWR1 Y19hZGRfc19xCiA7IG5lb25fZnBfcmVkdWNfYWRkX2QKQEAgLTEwMzMsNiArMTAzNCw3IEBAIChk ZWZpbmVfYXR0ciAidHlwZSIKICAgbmVvbl9mcF9taW5tYXhfZCxcCiAgIG5lb25fZnBfbWlubWF4 X2RfcSxcCiBcCisgIG5lb25fZnBfcmVkdWNfYWRkX2gsXAogICBuZW9uX2ZwX3JlZHVjX2FkZF9z LFwKICAgbmVvbl9mcF9yZWR1Y19hZGRfc19xLFwKICAgbmVvbl9mcF9yZWR1Y19hZGRfZCxcCkBA IC0xMjU3LDggKzEyNTksOCBAQCAoZGVmaW5lX2F0dHIgImlzX25lb25fdHlwZSIgInllcyxubyIK ICAgICAgICAgICBuZW9uX2ZwX2NvbXBhcmVfZCwgbmVvbl9mcF9jb21wYXJlX2RfcSwgbmVvbl9m cF9taW5tYXhfcyxcCiAgICAgICAgICAgbmVvbl9mcF9taW5tYXhfc19xLCBuZW9uX2ZwX21pbm1h eF9kLCBuZW9uX2ZwX21pbm1heF9kX3EsXAogICAgICAgICAgIG5lb25fZnBfbmVnX3MsIG5lb25f ZnBfbmVnX3NfcSwgbmVvbl9mcF9uZWdfZCwgbmVvbl9mcF9uZWdfZF9xLFwKLSAgICAgICAgICBu ZW9uX2ZwX3JlZHVjX2FkZF9zLCBuZW9uX2ZwX3JlZHVjX2FkZF9zX3EsIG5lb25fZnBfcmVkdWNf YWRkX2QsXAotICAgICAgICAgIG5lb25fZnBfcmVkdWNfYWRkX2RfcSwgbmVvbl9mcF9yZWR1Y19t aW5tYXhfcywKKyAgICAgICAgICBuZW9uX2ZwX3JlZHVjX2FkZF9oLCBuZW9uX2ZwX3JlZHVjX2Fk ZF9zLCBuZW9uX2ZwX3JlZHVjX2FkZF9zX3EsXAorICAgICAgICAgIG5lb25fZnBfcmVkdWNfYWRk X2QsIG5lb25fZnBfcmVkdWNfYWRkX2RfcSwgbmVvbl9mcF9yZWR1Y19taW5tYXhfcyxcCiAgICAg ICAgICAgbmVvbl9mcF9yZWR1Y19taW5tYXhfc19xLCBuZW9uX2ZwX3JlZHVjX21pbm1heF9kLFwK ICAgICAgICAgICBuZW9uX2ZwX3JlZHVjX21pbm1heF9kX3EsXAogICAgICAgICAgIG5lb25fZnBf Y3Z0X25hcnJvd19zX3EsIG5lb25fZnBfY3Z0X25hcnJvd19kX3EsXApkaWZmIC0tZ2l0IGEvZ2Nj L3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvc3ZlL3NscF8xLmMgYi9nY2MvdGVzdHN1aXRl L2djYy50YXJnZXQvYWFyY2g2NC9zdmUvc2xwXzEuYwppbmRleCAwN2Q3MWE2MzQxNGIxMDY2ZWE0 MzFlMjg3Mjg2YWQwNDg1MTU3MTFhLi5lNjAyMWM1YTQyNzQ4NzAxZTUzMjZhNWMzODdhMzlhMGJi YWRjOWU1IDEwMDY0NAotLS0gYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9zdmUv c2xwXzEuYworKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9zdmUvc2xwXzEu YwpAQCAtMzAsMTEgKzMwLDkgQEAgdmVjX3NscF8jI1RZUEUgKFRZUEUgKnJlc3RyaWN0IGEsIFRZ UEUgYiwgVFlQRSBjLCBpbnQgbikJXAogVEVTVF9BTEwgKFZFQ19QRVJNKQogCiAvKiBXZSBzaG91 bGQgdXNlIG9uZSBEVVAgZm9yIGVhY2ggb2YgdGhlIDgtLCAxNi0gYW5kIDMyLWJpdCB0eXBlcywK LSAgIGFsdGhvdWdoIHdlIGN1cnJlbnRseSB1c2UgTEQxUlcgZm9yIF9GbG9hdDE2LiAgV2Ugc2hv dWxkIHVzZSB0d28KLSAgIERVUHMgZm9yIGVhY2ggb2YgdGhlIHRocmVlIDY0LWJpdCB0eXBlcy4g ICovCisgICBXZSBzaG91bGQgdXNlIHR3byBEVVBzIGZvciBlYWNoIG9mIHRoZSB0aHJlZSA2NC1i aXQgdHlwZXMuICAqLwogLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtcdG1v dlx0elswLTldK1wuaCwgW2h3XX0gMiB9IH0gKi8KLS8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2Vt Ymxlci10aW1lcyB7XHRtb3ZcdHpbMC05XStcLnMsIFtzd119IDIgfSB9ICovCi0vKiB7IGRnLWZp bmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge1x0bGQxcndcdHpbMC05XStcLnMsIH0gMSB9IH0g Ki8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHRtb3ZcdHpbMC05XStc LnMsIFtzd119IDMgfSB9ICovCiAvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMg e1x0bW92XHR6WzAtOV0rXC5kLCBbZHhdfSA5IH0gfSAqLwogLyogeyBkZy1maW5hbCB7IHNjYW4t YXNzZW1ibGVyLXRpbWVzIHtcdHppcDFcdHpbMC05XStcLmQsIHpbMC05XStcLmQsIHpbMC05XStc LmRcbn0gMyB9IH0gKi8KIC8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci1ub3Qge1x0emlw Mlx0fSB9IH0gKi8KQEAgLTUzLDcgKzUxLDcgQEAgVEVTVF9BTEwgKFZFQ19QRVJNKQogLyogeyBk Zy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtcdHdoaWxlbG9cdHBbMC03XVwuc30gNiB9 IH0gKi8KIC8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHR3aGlsZWxvXHRw WzAtN11cLmR9IDYgfSB9ICovCiAvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItbm90IHtc dGxkcn0gfSB9ICovCi0vKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge1x0c3Ry fSAyIH0gfSAqLwotLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtcdHN0clx0 aFswLTldK30gMiB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci1ub3Qge1x0 c3RyfSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci1ub3Qge1x0c3RyXHRo WzAtOV0rfSB9IH0gKi8KIAogLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLW5vdCB7XHR1 cWRlY30gfSB9ICovCg== --_002_VI1PR08MB5325335D195073D1E5B2AB33FF009VI1PR08MB5325eurp_--