* [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
@ 2021-11-10 11:54 Tamar Christina
2021-11-10 18:37 ` Sandra Loosemore
0 siblings, 1 reply; 5+ messages in thread
From: Tamar Christina @ 2021-11-10 11:54 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, rguenther
[-- Attachment #1: Type: text/plain, Size: 2168 bytes --]
Hi All,
These test don't work on vector ISAs where the truth
type don't match the vector mode of the operation.
However I still want the tests to run on these
architectures but just turn off the ISA modes that
enable masks.
This thus turns off SVE is it's on and turns off
AVX512 if it's on.
Regtested on aarch64-none-linux-gnu with SVE on,
and x86_64-pc-linux-gnu with AVX512 on and no
issues.
Committed under the obvious rule.
Thanks,
Tamar
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-2.c: Turn of masks.
* gcc.dg/signbit-5.c: Likewise.
--- inline copy of patch --
diff --git a/gcc/testsuite/gcc.dg/signbit-2.c b/gcc/testsuite/gcc.dg/signbit-2.c
index fc0157cbc5c7996b481f2998bc30176c96a669bb..d8501e9b7a2d82b511ad0b3a44c0121d635972c0 100644
--- a/gcc/testsuite/gcc.dg/signbit-2.c
+++ b/gcc/testsuite/gcc.dg/signbit-2.c
@@ -1,6 +1,10 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps -fdump-tree-optimized" } */
+/* This test does not work when the truth type does not match vector type. */
+/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
+
#include <stdint.h>
void fun1(int32_t *x, int n)
@@ -15,5 +19,5 @@ void fun2(int32_t *x, int n)
x[i] = (-x[i]) >> 30;
}
-/* { dg-final { scan-tree-dump-times {\s+>\s+\{ 0, 0, 0, 0 \}} 1 optimized } } */
+/* { dg-final { scan-tree-dump {\s+>\s+\{ 0, 0, 0(, 0)+ \}} optimized } } */
/* { dg-final { scan-tree-dump-not {\s+>>\s+31} optimized } } */
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 22a92704773e3282759524b74d35196a477d43dd..2b119cdfda7d2888f914633c809b0aa7da5244b7 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -1,6 +1,11 @@
/* { dg-do run } */
/* { dg-options "-O3" } */
+/* This test does not work when the truth type does not match vector type. */
+/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
+
#include <stdint.h>
#include <limits.h>
#include <stdio.h>
--
[-- Attachment #2: rb15054.patch --]
[-- Type: text/x-diff, Size: 1588 bytes --]
diff --git a/gcc/testsuite/gcc.dg/signbit-2.c b/gcc/testsuite/gcc.dg/signbit-2.c
index fc0157cbc5c7996b481f2998bc30176c96a669bb..d8501e9b7a2d82b511ad0b3a44c0121d635972c0 100644
--- a/gcc/testsuite/gcc.dg/signbit-2.c
+++ b/gcc/testsuite/gcc.dg/signbit-2.c
@@ -1,6 +1,10 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps -fdump-tree-optimized" } */
+/* This test does not work when the truth type does not match vector type. */
+/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
+
#include <stdint.h>
void fun1(int32_t *x, int n)
@@ -15,5 +19,5 @@ void fun2(int32_t *x, int n)
x[i] = (-x[i]) >> 30;
}
-/* { dg-final { scan-tree-dump-times {\s+>\s+\{ 0, 0, 0, 0 \}} 1 optimized } } */
+/* { dg-final { scan-tree-dump {\s+>\s+\{ 0, 0, 0(, 0)+ \}} optimized } } */
/* { dg-final { scan-tree-dump-not {\s+>>\s+31} optimized } } */
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 22a92704773e3282759524b74d35196a477d43dd..2b119cdfda7d2888f914633c809b0aa7da5244b7 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -1,6 +1,11 @@
/* { dg-do run } */
/* { dg-options "-O3" } */
+/* This test does not work when the truth type does not match vector type. */
+/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
+
+
#include <stdint.h>
#include <limits.h>
#include <stdio.h>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
2021-11-10 11:54 [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks Tamar Christina
@ 2021-11-10 18:37 ` Sandra Loosemore
2021-11-10 18:53 ` Tamar Christina
0 siblings, 1 reply; 5+ messages in thread
From: Sandra Loosemore @ 2021-11-10 18:37 UTC (permalink / raw)
To: Tamar Christina, gcc-patches; +Cc: nd, rguenther
On 11/10/21 4:54 AM, Tamar Christina via Gcc-patches wrote:
> Hi All,
>
> These test don't work on vector ISAs where the truth
> type don't match the vector mode of the operation.
>
> However I still want the tests to run on these
> architectures but just turn off the ISA modes that
> enable masks.
>
> This thus turns off SVE is it's on and turns off
> AVX512 if it's on.
>
> Regtested on aarch64-none-linux-gnu with SVE on,
> and x86_64-pc-linux-gnu with AVX512 on and no
> issues.
>
> Committed under the obvious rule.
>
> Thanks,
> Tamar
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/signbit-2.c: Turn of masks.
> * gcc.dg/signbit-5.c: Likewise.
I'm seeing this failure on nios2-elf:
FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized "\\s+>\\s+{ 0,
0, 0, 0 }" 1
I don't understand what it is expecting to happen here. Should it be
skipped on this target, or restricted to ARM and x86? Adding some
comments to the testcase to explain the significance of that pattern
might be useful too.
-Sandra
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
2021-11-10 18:37 ` Sandra Loosemore
@ 2021-11-10 18:53 ` Tamar Christina
2021-11-10 20:03 ` Sandra Loosemore
0 siblings, 1 reply; 5+ messages in thread
From: Tamar Christina @ 2021-11-10 18:53 UTC (permalink / raw)
To: Sandra Loosemore, gcc-patches; +Cc: nd, rguenther
FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized "[file://\\s+]\\s+>\\s+{ 0,
0, 0, 0 }" 1
That's the old test which this patch has changed. Does it still fail with the new patch?
________________________________
From: Sandra Loosemore <sandra@codesourcery.com>
Sent: Wednesday, November 10, 2021 6:37 PM
To: Tamar Christina <Tamar.Christina@arm.com>; gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Cc: nd <nd@arm.com>; rguenther@suse.de <rguenther@suse.de>
Subject: Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
On 11/10/21 4:54 AM, Tamar Christina via Gcc-patches wrote:
> Hi All,
>
> These test don't work on vector ISAs where the truth
> type don't match the vector mode of the operation.
>
> However I still want the tests to run on these
> architectures but just turn off the ISA modes that
> enable masks.
>
> This thus turns off SVE is it's on and turns off
> AVX512 if it's on.
>
> Regtested on aarch64-none-linux-gnu with SVE on,
> and x86_64-pc-linux-gnu with AVX512 on and no
> issues.
>
> Committed under the obvious rule.
>
> Thanks,
> Tamar
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/signbit-2.c: Turn of masks.
> * gcc.dg/signbit-5.c: Likewise.
I'm seeing this failure on nios2-elf:
FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized "\\s+<file://\\s+>>\\s+{ 0,
0, 0, 0 }" 1
I don't understand what it is expecting to happen here. Should it be
skipped on this target, or restricted to ARM and x86? Adding some
comments to the testcase to explain the significance of that pattern
might be useful too.
-Sandra
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
2021-11-10 18:53 ` Tamar Christina
@ 2021-11-10 20:03 ` Sandra Loosemore
2021-11-11 13:24 ` Tamar Christina
0 siblings, 1 reply; 5+ messages in thread
From: Sandra Loosemore @ 2021-11-10 20:03 UTC (permalink / raw)
To: Tamar Christina, gcc-patches; +Cc: nd, rguenther
[-- Attachment #1: Type: text/plain, Size: 629 bytes --]
On 11/10/21 11:53 AM, Tamar Christina wrote:
> FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized
> "[file://\\s+]\\s+>\\s+{ 0,
> 0, 0, 0 }" 1
>
> That's the old test which this patch has changed. Does it still fail
> with the new patch?
My test results are indeed from a couple days ago. But, I looked at
your new modifications to this test, and still don't see anything like
the pattern it's looking for, or understand what output you expect to be
happening here. Is the whole test specific to vector ISAs, and not just
your recent changes to it? I've attached the .optimized dump I got on
nios2-elf.
-Sandra
[-- Attachment #2: signbit-2.c.250t.optimized --]
[-- Type: text/plain, Size: 2028 bytes --]
;; Function fun1 (fun1, funcdef_no=0, decl_uid=1561, cgraph_uid=1, symbol_order=0)
Removing basic block 6
Removing basic block 7
Removing basic block 8
void fun1 (int32_t * x, int n)
{
unsigned int ivtmp.11;
long int _4;
long int _6;
unsigned int _9;
_Bool _15;
unsigned int _16;
int _17;
unsigned int _21;
long int _22;
void * _23;
<bb 2> [local count: 118111600]:
_17 = n_11(D) & -16;
if (_17 > 0)
goto <bb 3>; [89.00%]
else
goto <bb 5>; [11.00%]
<bb 3> [local count: 105119324]:
ivtmp.11_24 = (unsigned int) x_12(D);
_21 = (unsigned int) _17;
_16 = _21 * 4;
_9 = _16 + ivtmp.11_24;
<bb 4> [local count: 955630225]:
# ivtmp.11_20 = PHI <ivtmp.11_25(4), ivtmp.11_24(3)>
_23 = (void *) ivtmp.11_20;
_4 = MEM[(int32_t *)_23];
_15 = _4 > 0;
_22 = (long int) _15;
_6 = -_22;
MEM[(int32_t *)_23] = _6;
ivtmp.11_25 = ivtmp.11_20 + 4;
if (_9 != ivtmp.11_25)
goto <bb 4>; [89.00%]
else
goto <bb 5>; [11.00%]
<bb 5> [local count: 118111600]:
return;
}
;; Function fun2 (fun2, funcdef_no=1, decl_uid=1570, cgraph_uid=2, symbol_order=1)
Removing basic block 6
Removing basic block 7
Removing basic block 8
void fun2 (int32_t * x, int n)
{
unsigned int ivtmp.19;
long int _4;
long int _5;
long int _6;
unsigned int _9;
unsigned int _16;
int _17;
unsigned int _21;
void * _23;
<bb 2> [local count: 118111600]:
_17 = n_11(D) & -16;
if (_17 > 0)
goto <bb 3>; [89.00%]
else
goto <bb 5>; [11.00%]
<bb 3> [local count: 105119324]:
ivtmp.19_24 = (unsigned int) x_12(D);
_21 = (unsigned int) _17;
_16 = _21 * 4;
_9 = _16 + ivtmp.19_24;
<bb 4> [local count: 955630225]:
# ivtmp.19_20 = PHI <ivtmp.19_25(4), ivtmp.19_24(3)>
_23 = (void *) ivtmp.19_20;
_4 = MEM[(int32_t *)_23];
_5 = -_4;
_6 = _5 >> 30;
MEM[(int32_t *)_23] = _6;
ivtmp.19_25 = ivtmp.19_20 + 4;
if (_9 != ivtmp.19_25)
goto <bb 4>; [89.00%]
else
goto <bb 5>; [11.00%]
<bb 5> [local count: 118111600]:
return;
}
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
2021-11-10 20:03 ` Sandra Loosemore
@ 2021-11-11 13:24 ` Tamar Christina
0 siblings, 0 replies; 5+ messages in thread
From: Tamar Christina @ 2021-11-11 13:24 UTC (permalink / raw)
To: Sandra Loosemore, gcc-patches; +Cc: nd, rguenther
Ah yes that particular test checks the vector code.
I see that the function wasn't vectorized but that the scalar replacement was done.
_15 = _4 > 0;
So the test is checking if (-x >> bitsize-1) gets optimized to -(x > 0)
I see that the replacement was made on the scalar correctly so I will modify
The test to check for either the vector is vect_int or the scalar replacement
if not.
Cheers,
Tamar
________________________________
From: Sandra Loosemore <sandra@codesourcery.com>
Sent: Wednesday, November 10, 2021 8:03 PM
To: Tamar Christina <Tamar.Christina@arm.com>; gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Cc: nd <nd@arm.com>; rguenther@suse.de <rguenther@suse.de>
Subject: Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
On 11/10/21 11:53 AM, Tamar Christina wrote:
> FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized
> "[file://\\s+]\\s+<file://s+]//s+>>\\s+{ 0,
> 0, 0, 0 }" 1
>
> That's the old test which this patch has changed. Does it still fail
> with the new patch?
My test results are indeed from a couple days ago. But, I looked at
your new modifications to this test, and still don't see anything like
the pattern it's looking for, or understand what output you expect to be
happening here. Is the whole test specific to vector ISAs, and not just
your recent changes to it? I've attached the .optimized dump I got on
nios2-elf.
-Sandra
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-11-10 11:54 [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks Tamar Christina
2021-11-10 18:37 ` Sandra Loosemore
2021-11-10 18:53 ` Tamar Christina
2021-11-10 20:03 ` Sandra Loosemore
2021-11-11 13:24 ` Tamar Christina
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