From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 1DBDA3858424 for ; Tue, 8 Nov 2022 10:06:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1DBDA3858424 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1667901973; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZQE0XxpPClr9+2KUnFAs780xsqZiygw6ee2Hx6BVNrg=; b=GnQYx4HiLlweYaJsiTx2bXQSJ4kQFPBrX/57xoFggx4Uvi1NJyYBqZdgTesMS8CjAMYNme cT/hr5zOAyZEySMfVoJNkMXi/LTHhoPnIc3TlHVxk7hxjQdm5OtFlxhpGPem5a5lm8ej24 PNV5myn2OD2Aam2gWLEjPEJp1TKCyYs= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-408-JyzMeQN-OTOvKacXsjGD8A-1; Tue, 08 Nov 2022 05:06:12 -0500 X-MC-Unique: JyzMeQN-OTOvKacXsjGD8A-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1B1B93811F34; Tue, 8 Nov 2022 10:06:12 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.193.252]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 80FCA140EBF3; Tue, 8 Nov 2022 10:06:11 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 2A8A68862240094 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Tue, 8 Nov 2022 11:06:08 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 2A8A667n2240093; Tue, 8 Nov 2022 11:06:06 +0100 Date: Tue, 8 Nov 2022 11:06:06 +0100 From: Jakub Jelinek To: Haochen Jiang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, Richard.Earnshaw@foss.arm.com, segher@kernel.crashing.org Subject: Re: [PATCH] Support Intel prefetchit0/t1 Message-ID: Reply-To: Jakub Jelinek References: <20221104074632.19951-1-haochen.jiang@intel.com> MIME-Version: 1.0 In-Reply-To: <20221104074632.19951-1-haochen.jiang@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP,WEIRD_PORT autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Nov 04, 2022 at 03:46:32PM +0800, Haochen Jiang via Gcc-patches wrote: > We will take back the patches which add a new parameter on original > builtin_prefetch and implement instruction prefetch on that. > > Also we consider that since we will only do that on specific backend, > no need to add a new rtl for that. > > This patch will only support instructions prefetch for x86 backend. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? The gcc.target/i386/prefetchi-4.c testcase ICEs for me on i686-linux. Can be reproduced even on x86_64, with: ./cc1 -quiet -m32 -march=pentiumpro prefetchi-4.c -isystem include/ during RTL pass: expand prefetchi-4.c: In function ‘prefetch_test’: prefetchi-4.c:11:3: internal compiler error: in gen_prefetch, at config/i386/i386.md:23913 11 | __builtin_ia32_prefetch (p, 0, 3, 0); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0x1b92416 gen_prefetch(rtx_def*, rtx_def*, rtx_def*) ../../gcc/config/i386/i386.md:23913 0x141dcf3 ix86_expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int) ../../gcc/config/i386/i386-expand.cc:13077 0x60deb4 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int) ../../gcc/builtins.cc:7321 0x80803d expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool) ../../gcc/expr.cc:11865 0x7fa4d5 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool) ../../gcc/expr.cc:9000 0x648c12 expand_expr ../../gcc/expr.h:310 0x651c17 expand_call_stmt ../../gcc/cfgexpand.cc:2831 0x655709 expand_gimple_stmt_1 ../../gcc/cfgexpand.cc:3880 0x655d93 expand_gimple_stmt ../../gcc/cfgexpand.cc:4044 0x65e061 expand_gimple_basic_block ../../gcc/cfgexpand.cc:6096 0x660575 execute ../../gcc/cfgexpand.cc:6822 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See for instructions. The ICE is on gcc_assert (TARGET_3DNOW); operands[2] = GEN_INT (3); The expander has "TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1" condition and for write handles all those different ISAs, so gcc_assert (TARGET_3DNOW); at the end only asserts the obvious that the expander condition had to be satisfied. But for !write, it only has: if (TARGET_PREFETCH_SSE) ; else { gcc_assert (TARGET_3DNOW); operands[2] = GEN_INT (3); } and here I don't understand how it can work, because if !TARGET_3DNOW && !TARGET_PREFETCH_SSE, but TARGET_PRFCHW || TARGET_PREFETCHWT1 then it clearly ICEs. Both of the latter ISAs can be enabled/disabled individually without dependencies. It is unclear what exactly changed though, because the prefetch pattern has not changed, but it didn't ICE before that commit. Jakub