From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id D98BD3857BA4 for ; Mon, 14 Nov 2022 08:35:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D98BD3857BA4 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1668414907; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=npC4AFQ6PdaDEfmcBMlwq7JoXkzctj5gcmR4ALZX1QM=; b=SF/fHE+LQjZQm+ImuV8+j881I8jDlAn6DqtF3z97WqoIlcVMa7ZMru/F8rFBilqah4rTOM WFfDwWUtfL/ozvM71v9pvn/xx9zae8keSqC8hZMxEngbN3IaEL7EDPxe8huPq9bB4T/S40 MHGMvKhwvsflyxqdPGJMohZ+UCTXlh0= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-218-vwGh0mBEOIyivsOsHQ06pA-1; Mon, 14 Nov 2022 03:35:04 -0500 X-MC-Unique: vwGh0mBEOIyivsOsHQ06pA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id D0D863815D2B; Mon, 14 Nov 2022 08:35:03 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.38]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3B6D0111F3C1; Mon, 14 Nov 2022 08:35:03 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 2AE8YvDg2822617 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 14 Nov 2022 09:34:58 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 2AE8YsY72822615; Mon, 14 Nov 2022 09:34:54 +0100 Date: Mon, 14 Nov 2022 09:34:54 +0100 From: Jakub Jelinek To: Xi Ruoyao Cc: Uros Bizjak , Mayshao-oc , Richard Biener , Jeff Law , gcc-patches@gcc.gnu.org, Florian Weimer , "H.J. Lu" Subject: Re: [PATCH] libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688] Message-ID: Reply-To: Jakub Jelinek References: <0fa5e4e5ce325a8e432e9e0bd2e598aa48666501.camel@xry111.site> MIME-Version: 1.0 In-Reply-To: <0fa5e4e5ce325a8e432e9e0bd2e598aa48666501.camel@xry111.site> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 14, 2022 at 04:19:48PM +0800, Xi Ruoyao wrote: > > > --- libatomic/config/x86/init.c.jj      2022-03-17 > > > 18:48:56.708723194 +0100 > > > +++ libatomic/config/x86/init.c 2022-11-13 18:23:26.315440071 -1200 > > > @@ -34,18 +34,6 @@ __libat_feat1_init (void) > > >    unsigned int eax, ebx, ecx, edx; > > >    FEAT1_REGISTER = 0; > > >    __get_cpuid (1, &eax, &ebx, &ecx, &edx); > > > -#ifdef __x86_64__ > > > -  if ((FEAT1_REGISTER & (bit_AVX | bit_CMPXCHG16B)) > > > -      == (bit_AVX | bit_CMPXCHG16B)) > > > -    { > > > -      /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte > > > aligned address > > > -        is atomic, but so far we don't have this guarantee from > > > AMD.  */ > > > -      unsigned int ecx2 = 0; > > > -      __get_cpuid (0, &eax, &ebx, &ecx2, &edx); > > > -      if (ecx2 != signature_INTEL_ecx) > > > -       FEAT1_REGISTER &= ~bit_AVX; > > > > We still need this, but also bypass it for AMD signature. There are > > other vendors than Intel and AMD. > > Mayshao: how about the status of this feature on Zhaoxin product lines? > IIRC they support AVX (but disabled by default in GCC for Lujiazui), but > we don't know if they make the guarantee about atomicity of 16B aligned > access. I did the change on the assumption that only Intel and AMD implement AVX. Looking around, I'm afraid Zhaoxin Zhangjiang/Wudaokou/Lujiazui and VIA Eden C and VIA Nano C CPUs do support AVX too, the question is if they implement CMPXCHG16B too. >From what is in i386-common.cc, none of non-Intel CPUs in there have PTA_AVX and only Lujiazui has CX16. But that doesn't need to match what the HW actually does and one can just compile with -mcx16 -mavx -m64 rather than using some -march=whatever. Sure, can change the check so that it checks for AMD too for now and therefore discard the sync.md patch, the question is whom do we talk at Zhaoxin and VIA and if there are any further other CX16+AVX CPUs Jakub