* [PATCH] Move xx* builtins to vsx.md.
@ 2021-08-13 4:20 Michael Meissner
2021-08-18 20:01 ` Bill Schmidt
2021-08-18 20:42 ` David Edelsohn
0 siblings, 2 replies; 6+ messages in thread
From: Michael Meissner @ 2021-08-13 4:20 UTC (permalink / raw)
To: gcc-patches, Michael Meissner, Segher Boessenkool,
David Edelsohn, Bill Schmidt, Peter Bergner, Will Schmidt
Move xx* builtins to vsx.md.
I originally posted this patch in May. It needed a slight tune up as the
souces have changed, so I'm reposting it now.
I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since
the XX instructions can take both traditional floating point and Altivec
registers, these built-in functions should be in vsx.md.
This patch just moves the insns from altivec.md to vsx.md.
I also moved the VM3 mode iterator and VM3_char mode attribute from altivec.md
to vsx.md, since the only use of these were for the XXBLEND insns.
I have built little endian power9 compilers, little endian power10 compilers,
and big endian power8 compilers with this patch applied, and there were no
regressions. Can I apply this patch to the master branch?
Note this patch assumes the previous patch:
Fix xxeval predicates (PR 99921).
has been applied.
2021-08-12 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
(UNSPEC_XXSPLTIW): Move to vsx.md.
(UNSPEC_XXSPLTID): Move to vsx.md.
(UNSPEC_XXSPLTI32DX): Move to vsx.md.
(UNSPEC_XXBLEND): Move to vsx.md.
(UNSPEC_XXPERMX): Move to vsx.md.
(VM3): Move to vsx.md.
(VM3_char): Move to vsx.md.
(xxspltiw_v4si): Move to vsx.md.
(xxspltiw_v4sf): Move to vsx.md.
(xxspltiw_v4sf_inst): Move to vsx.md.
(xxspltidp_v2df): Move to vsx.md.
(xxspltidp_v2df_inst): Move to vsx.md.
(xxsplti32dx_v4si_inst): Move to vsx.md.
(xxsplti32dx_v4sf): Move to vsx.md.
(xxsplti32dx_v4sf_inst): Move to vsx.md.
(xxblend_<mode>): Move to vsx.md.
(xxpermx): Move to vsx.md.
(xxpermx_inst): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(UNSPEC_XXSPLTIW): Move from altivec.md.
(UNSPEC_XXSPLTID): Move from altivec.md.
(UNSPEC_XXSPLTI32DX): Move from altivec.md.
(UNSPEC_XXBLEND): Move from altivec.md.
(UNSPEC_XXPERMX): Move from altivec.md.
(VM3): Move from altivec.md.
(VM3_char): Move from altivec.md.
(xxspltiw_v4si): Move from altivec.md.
(xxspltiw_v4sf): Move from altivec.md.
(xxspltiw_v4sf_inst): Move from altivec.md.
(xxspltidp_v2df): Move from altivec.md.
(xxspltidp_v2df_inst): Move from altivec.md.
(xxsplti32dx_v4si_inst): Move from altivec.md.
(xxsplti32dx_v4sf): Move from altivec.md.
(xxsplti32dx_v4sf_inst): Move from altivec.md.
(xxblend_<mode>): Move from altivec.md.
(xxpermx): Move from altivec.md.
(xxpermx_inst): Move from altivec.md.
---
gcc/config/rs6000/altivec.md | 197 ---------------------------------
gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++
2 files changed, 206 insertions(+), 197 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fd86c300981..2c73ddea823 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,16 +175,10 @@ (define_c_enum "unspec"
UNSPEC_VPEXTD
UNSPEC_VCLRLB
UNSPEC_VCLRRB
- UNSPEC_XXEVAL
UNSPEC_VSTRIR
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXSPLTIW
- UNSPEC_XXSPLTID
- UNSPEC_XXSPLTI32DX
- UNSPEC_XXBLEND
- UNSPEC_XXPERMX
])
(define_c_enum "unspecv"
@@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-;; Like VM2, just do char, short, int, long, float and double
-(define_mode_iterator VM3 [V4SI
- V8HI
- V16QI
- V4SF
- V2DF
- V2DI])
-
-(define_mode_attr VM3_char [(V2DI "d")
- (V4SI "w")
- (V8HI "h")
- (V16QI "b")
- (V2DF "d")
- (V4SF "w")])
-
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -859,170 +838,6 @@ (define_insn "vs<SLDB_lr>db_<mode>"
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxspltiw_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxspltiw_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
- DONE;
-})
-
-(define_insn "xxspltiw_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxspltidp_v2df"
- [(set (match_operand:V2DF 0 "register_operand" )
- (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
- UNSPEC_XXSPLTID))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- rs6000_emit_xxspltidp_v2df (operands[0], value);
- DONE;
-})
-
-(define_insn "xxspltidp_v2df_inst"
- [(set (match_operand:V2DF 0 "register_operand" "=wa")
- (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTID))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxsplti32dx_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
-{
- int index = INTVAL (operands[2]);
-
- if (!BYTES_BIG_ENDIAN)
- index = 1 - index;
-
- emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
- GEN_INT (index), operands[3]));
- DONE;
-}
- [(set_attr "type" "vecsimple")])
-
-(define_insn "xxsplti32dx_v4si_inst"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxsplti32dx_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SF 3 "const_double_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
-{
- int index = INTVAL (operands[2]);
- long value = rs6000_const_f32_to_i32 (operands[3]);
- if (!BYTES_BIG_ENDIAN)
- index = 1 - index;
-
- emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
- GEN_INT (index), GEN_INT (value)));
- DONE;
-})
-
-(define_insn "xxsplti32dx_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VM3 0 "register_operand" "=wa")
- (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
- (match_operand:VM3 2 "register_operand" "wa")
- (match_operand:VM3 3 "register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxpermx"
- [(set (match_operand:V2DI 0 "register_operand" "+wa")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
- (match_operand:V2DI 2 "register_operand" "wa")
- (match_operand:V16QI 3 "register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_xxpermx_inst (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- else
- {
- /* Reverse value of byte element indexes by XORing with 0xFF.
- Reverse the 32-byte section identifier match by subracting bits [0:2]
- of elemet from 7. */
- int value = INTVAL (operands[4]);
- rtx vreg = gen_reg_rtx (V16QImode);
-
- emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
- emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
- value = 7 - value;
- emit_insn (gen_xxpermx_inst (operands[0], operands[2],
- operands[1], operands[3],
- GEN_INT (value)));
- }
-
- DONE;
-}
- [(set_attr "type" "vecsimple")])
-
-(define_insn "xxpermx_inst"
- [(set (match_operand:V2DI 0 "register_operand" "+v")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
- (match_operand:V2DI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")
- (match_operand:QI 4 "u3bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
- "xxpermx %x0,%x1,%x2,%x3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
@@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi"
[(set_attr "type" "vecperm")
(set_attr "isa" "p9v,*")])
-(define_insn "xxeval"
- [(set (match_operand:V2DI 0 "register_operand" "=wa")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
- (match_operand:V2DI 2 "register_operand" "wa")
- (match_operand:V2DI 3 "register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXEVAL))]
- "TARGET_POWER10"
- "xxeval %0,%1,%2,%3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vec_unpacku_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6f6fc0bd835..cacdd0d4cc8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -372,6 +372,12 @@ (define_c_enum "unspec"
UNSPEC_REPLACE_UN
UNSPEC_VDIVES
UNSPEC_VDIVEU
+ UNSPEC_XXEVAL
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
+ UNSPEC_XXSPLTI32DX
+ UNSPEC_XXBLEND
+ UNSPEC_XXPERMX
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2")
(define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12")
(V2DI "8") (V2DF "8")])
+;; Like VM2 in altivec.md, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
+
;; VSX moves
;; The patterns for LE permuted loads and stores come before the general
@@ -6383,3 +6405,187 @@ (define_insn "mulv2di3"
"TARGET_POWER10"
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+
+\f
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXSPLTIDP built-in function support
+(define_expand "xxspltidp_v2df"
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ rs6000_emit_xxspltidp_v2df (operands[0], value);
+ DONE;
+})
+
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXSPLTI32DX built-in function support
+(define_expand "xxsplti32dx_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+{
+ int index = INTVAL (operands[2]);
+
+ if (!BYTES_BIG_ENDIAN)
+ index = 1 - index;
+
+ emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
+ GEN_INT (index), operands[3]));
+ DONE;
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "xxsplti32dx_v4si_inst"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+ "xxsplti32dx %x0,%2,%3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxsplti32dx_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SF 3 "const_double_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+{
+ int index = INTVAL (operands[2]);
+ long value = rs6000_const_f32_to_i32 (operands[3]);
+ if (!BYTES_BIG_ENDIAN)
+ index = 1 - index;
+
+ emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
+ GEN_INT (index), GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxsplti32dx_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+ "xxsplti32dx %x0,%2,%3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXBLEND built-in function support
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
+ (match_operand:VM3 2 "register_operand" "wa")
+ (match_operand:VM3 3 "register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXPERMX built-in function support
+(define_expand "xxpermx"
+ [(set (match_operand:V2DI 0 "register_operand" "+wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
+ (match_operand:V2DI 2 "register_operand" "wa")
+ (match_operand:V16QI 3 "register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+{
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_xxpermx_inst (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
+ else
+ {
+ /* Reverse value of byte element indexes by XORing with 0xFF.
+ Reverse the 32-byte section identifier match by subracting bits [0:2]
+ of elemet from 7. */
+ int value = INTVAL (operands[4]);
+ rtx vreg = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
+ emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
+ value = 7 - value;
+ emit_insn (gen_xxpermx_inst (operands[0], operands[2],
+ operands[1], operands[3],
+ GEN_INT (value)));
+ }
+
+ DONE;
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "xxpermx_inst"
+ [(set (match_operand:V2DI 0 "register_operand" "+v")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
+ (match_operand:V2DI 2 "register_operand" "v")
+ (match_operand:V16QI 3 "register_operand" "v")
+ (match_operand:QI 4 "u3bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+ "xxpermx %x0,%x1,%x2,%x3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXEVAL built-in function support
+(define_insn "xxeval"
+ [(set (match_operand:V2DI 0 "register_operand" "=wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
+ (match_operand:V2DI 2 "register_operand" "wa")
+ (match_operand:V2DI 3 "register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXEVAL))]
+ "TARGET_POWER10"
+ "xxeval %0,%1,%2,%3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
--
2.31.1
---
gcc/config/rs6000/altivec.md | 197 ---------------------------------
gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++
2 files changed, 206 insertions(+), 197 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fd86c300981..2c73ddea823 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,16 +175,10 @@ (define_c_enum "unspec"
UNSPEC_VPEXTD
UNSPEC_VCLRLB
UNSPEC_VCLRRB
- UNSPEC_XXEVAL
UNSPEC_VSTRIR
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXSPLTIW
- UNSPEC_XXSPLTID
- UNSPEC_XXSPLTI32DX
- UNSPEC_XXBLEND
- UNSPEC_XXPERMX
])
(define_c_enum "unspecv"
@@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-;; Like VM2, just do char, short, int, long, float and double
-(define_mode_iterator VM3 [V4SI
- V8HI
- V16QI
- V4SF
- V2DF
- V2DI])
-
-(define_mode_attr VM3_char [(V2DI "d")
- (V4SI "w")
- (V8HI "h")
- (V16QI "b")
- (V2DF "d")
- (V4SF "w")])
-
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -859,170 +838,6 @@ (define_insn "vs<SLDB_lr>db_<mode>"
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxspltiw_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxspltiw_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
- DONE;
-})
-
-(define_insn "xxspltiw_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxspltidp_v2df"
- [(set (match_operand:V2DF 0 "register_operand" )
- (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
- UNSPEC_XXSPLTID))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- rs6000_emit_xxspltidp_v2df (operands[0], value);
- DONE;
-})
-
-(define_insn "xxspltidp_v2df_inst"
- [(set (match_operand:V2DF 0 "register_operand" "=wa")
- (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTID))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxsplti32dx_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
-{
- int index = INTVAL (operands[2]);
-
- if (!BYTES_BIG_ENDIAN)
- index = 1 - index;
-
- emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
- GEN_INT (index), operands[3]));
- DONE;
-}
- [(set_attr "type" "vecsimple")])
-
-(define_insn "xxsplti32dx_v4si_inst"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxsplti32dx_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SF 3 "const_double_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
-{
- int index = INTVAL (operands[2]);
- long value = rs6000_const_f32_to_i32 (operands[3]);
- if (!BYTES_BIG_ENDIAN)
- index = 1 - index;
-
- emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
- GEN_INT (index), GEN_INT (value)));
- DONE;
-})
-
-(define_insn "xxsplti32dx_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:QI 2 "u1bit_cint_operand" "n")
- (match_operand:SI 3 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTI32DX))]
- "TARGET_POWER10"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VM3 0 "register_operand" "=wa")
- (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
- (match_operand:VM3 2 "register_operand" "wa")
- (match_operand:VM3 3 "register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_expand "xxpermx"
- [(set (match_operand:V2DI 0 "register_operand" "+wa")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
- (match_operand:V2DI 2 "register_operand" "wa")
- (match_operand:V16QI 3 "register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_xxpermx_inst (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- else
- {
- /* Reverse value of byte element indexes by XORing with 0xFF.
- Reverse the 32-byte section identifier match by subracting bits [0:2]
- of elemet from 7. */
- int value = INTVAL (operands[4]);
- rtx vreg = gen_reg_rtx (V16QImode);
-
- emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
- emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
- value = 7 - value;
- emit_insn (gen_xxpermx_inst (operands[0], operands[2],
- operands[1], operands[3],
- GEN_INT (value)));
- }
-
- DONE;
-}
- [(set_attr "type" "vecsimple")])
-
-(define_insn "xxpermx_inst"
- [(set (match_operand:V2DI 0 "register_operand" "+v")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
- (match_operand:V2DI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")
- (match_operand:QI 4 "u3bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
- "xxpermx %x0,%x1,%x2,%x3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
@@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi"
[(set_attr "type" "vecperm")
(set_attr "isa" "p9v,*")])
-(define_insn "xxeval"
- [(set (match_operand:V2DI 0 "register_operand" "=wa")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
- (match_operand:V2DI 2 "register_operand" "wa")
- (match_operand:V2DI 3 "register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXEVAL))]
- "TARGET_POWER10"
- "xxeval %0,%1,%2,%3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vec_unpacku_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 441735df9c3..e4ca6e94d49 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -372,6 +372,12 @@ (define_c_enum "unspec"
UNSPEC_REPLACE_UN
UNSPEC_VDIVES
UNSPEC_VDIVEU
+ UNSPEC_XXEVAL
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
+ UNSPEC_XXSPLTI32DX
+ UNSPEC_XXBLEND
+ UNSPEC_XXPERMX
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2")
(define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12")
(V2DI "8") (V2DF "8")])
+;; Like VM2 in altivec.md, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
+
;; VSX moves
;; The patterns for LE permuted loads and stores come before the general
@@ -6383,3 +6405,187 @@ (define_insn "mulv2di3"
"TARGET_POWER10"
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+
+\f
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXSPLTIDP built-in function support
+(define_expand "xxspltidp_v2df"
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ rs6000_emit_xxspltidp_v2df (operands[0], value);
+ DONE;
+})
+
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXSPLTI32DX built-in function support
+(define_expand "xxsplti32dx_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+{
+ int index = INTVAL (operands[2]);
+
+ if (!BYTES_BIG_ENDIAN)
+ index = 1 - index;
+
+ emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
+ GEN_INT (index), operands[3]));
+ DONE;
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "xxsplti32dx_v4si_inst"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+ "xxsplti32dx %x0,%2,%3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxsplti32dx_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SF 3 "const_double_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+{
+ int index = INTVAL (operands[2]);
+ long value = rs6000_const_f32_to_i32 (operands[3]);
+ if (!BYTES_BIG_ENDIAN)
+ index = 1 - index;
+
+ emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
+ GEN_INT (index), GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxsplti32dx_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:QI 2 "u1bit_cint_operand" "n")
+ (match_operand:SI 3 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTI32DX))]
+ "TARGET_POWER10"
+ "xxsplti32dx %x0,%2,%3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXBLEND built-in function support
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
+ (match_operand:VM3 2 "register_operand" "wa")
+ (match_operand:VM3 3 "register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXPERMX built-in function support
+(define_expand "xxpermx"
+ [(set (match_operand:V2DI 0 "register_operand" "+wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
+ (match_operand:V2DI 2 "register_operand" "wa")
+ (match_operand:V16QI 3 "register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+{
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_xxpermx_inst (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
+ else
+ {
+ /* Reverse value of byte element indexes by XORing with 0xFF.
+ Reverse the 32-byte section identifier match by subracting bits [0:2]
+ of elemet from 7. */
+ int value = INTVAL (operands[4]);
+ rtx vreg = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
+ emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
+ value = 7 - value;
+ emit_insn (gen_xxpermx_inst (operands[0], operands[2],
+ operands[1], operands[3],
+ GEN_INT (value)));
+ }
+
+ DONE;
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "xxpermx_inst"
+ [(set (match_operand:V2DI 0 "register_operand" "+v")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
+ (match_operand:V2DI 2 "register_operand" "v")
+ (match_operand:V16QI 3 "register_operand" "v")
+ (match_operand:QI 4 "u3bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+ "xxpermx %x0,%x1,%x2,%x3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+;; XXEVAL built-in function support
+(define_insn "xxeval"
+ [(set (match_operand:V2DI 0 "register_operand" "=wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
+ (match_operand:V2DI 2 "register_operand" "wa")
+ (match_operand:V2DI 3 "register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXEVAL))]
+ "TARGET_POWER10"
+ "xxeval %0,%1,%2,%3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
--
2.31.1
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Move xx* builtins to vsx.md.
2021-08-13 4:20 [PATCH] Move xx* builtins to vsx.md Michael Meissner
@ 2021-08-18 20:01 ` Bill Schmidt
2021-08-18 20:42 ` David Edelsohn
1 sibling, 0 replies; 6+ messages in thread
From: Bill Schmidt @ 2021-08-18 20:01 UTC (permalink / raw)
To: Michael Meissner, gcc-patches, Segher Boessenkool,
David Edelsohn, Peter Bergner, Will Schmidt
Hi Mike,
On 8/12/21 11:20 PM, Michael Meissner wrote:
> Move xx* builtins to vsx.md.
>
> I originally posted this patch in May. It needed a slight tune up as the
> souces have changed, so I'm reposting it now.
>
> I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
> xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since
> the XX instructions can take both traditional floating point and Altivec
> registers, these built-in functions should be in vsx.md.
>
> This patch just moves the insns from altivec.md to vsx.md.
>
> I also moved the VM3 mode iterator and VM3_char mode attribute from altivec.md
> to vsx.md, since the only use of these were for the XXBLEND insns.
>
> I have built little endian power9 compilers, little endian power10 compilers,
> and big endian power8 compilers with this patch applied, and there were no
> regressions. Can I apply this patch to the master branch?
>
> Note this patch assumes the previous patch:
>
> Fix xxeval predicates (PR 99921).
>
> has been applied.
This looks straightforward and fine to me. Recommend approval...
Thanks,
Bill
>
> 2021-08-12 Michael Meissner <meissner@linux.ibm.com>
>
> gcc/
> * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
> (UNSPEC_XXSPLTIW): Move to vsx.md.
> (UNSPEC_XXSPLTID): Move to vsx.md.
> (UNSPEC_XXSPLTI32DX): Move to vsx.md.
> (UNSPEC_XXBLEND): Move to vsx.md.
> (UNSPEC_XXPERMX): Move to vsx.md.
> (VM3): Move to vsx.md.
> (VM3_char): Move to vsx.md.
> (xxspltiw_v4si): Move to vsx.md.
> (xxspltiw_v4sf): Move to vsx.md.
> (xxspltiw_v4sf_inst): Move to vsx.md.
> (xxspltidp_v2df): Move to vsx.md.
> (xxspltidp_v2df_inst): Move to vsx.md.
> (xxsplti32dx_v4si_inst): Move to vsx.md.
> (xxsplti32dx_v4sf): Move to vsx.md.
> (xxsplti32dx_v4sf_inst): Move to vsx.md.
> (xxblend_<mode>): Move to vsx.md.
> (xxpermx): Move to vsx.md.
> (xxpermx_inst): Move to vsx.md.
> * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
> (UNSPEC_XXSPLTIW): Move from altivec.md.
> (UNSPEC_XXSPLTID): Move from altivec.md.
> (UNSPEC_XXSPLTI32DX): Move from altivec.md.
> (UNSPEC_XXBLEND): Move from altivec.md.
> (UNSPEC_XXPERMX): Move from altivec.md.
> (VM3): Move from altivec.md.
> (VM3_char): Move from altivec.md.
> (xxspltiw_v4si): Move from altivec.md.
> (xxspltiw_v4sf): Move from altivec.md.
> (xxspltiw_v4sf_inst): Move from altivec.md.
> (xxspltidp_v2df): Move from altivec.md.
> (xxspltidp_v2df_inst): Move from altivec.md.
> (xxsplti32dx_v4si_inst): Move from altivec.md.
> (xxsplti32dx_v4sf): Move from altivec.md.
> (xxsplti32dx_v4sf_inst): Move from altivec.md.
> (xxblend_<mode>): Move from altivec.md.
> (xxpermx): Move from altivec.md.
> (xxpermx_inst): Move from altivec.md.
> ---
> gcc/config/rs6000/altivec.md | 197 ---------------------------------
> gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++
> 2 files changed, 206 insertions(+), 197 deletions(-)
>
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index fd86c300981..2c73ddea823 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -175,16 +175,10 @@ (define_c_enum "unspec"
> UNSPEC_VPEXTD
> UNSPEC_VCLRLB
> UNSPEC_VCLRRB
> - UNSPEC_XXEVAL
> UNSPEC_VSTRIR
> UNSPEC_VSTRIL
> UNSPEC_SLDB
> UNSPEC_SRDB
> - UNSPEC_XXSPLTIW
> - UNSPEC_XXSPLTID
> - UNSPEC_XXSPLTI32DX
> - UNSPEC_XXBLEND
> - UNSPEC_XXPERMX
> ])
>
> (define_c_enum "unspecv"
> @@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI
> (KF "FLOAT128_VECTOR_P (KFmode)")
> (TF "FLOAT128_VECTOR_P (TFmode)")])
>
> -;; Like VM2, just do char, short, int, long, float and double
> -(define_mode_iterator VM3 [V4SI
> - V8HI
> - V16QI
> - V4SF
> - V2DF
> - V2DI])
> -
> -(define_mode_attr VM3_char [(V2DI "d")
> - (V4SI "w")
> - (V8HI "h")
> - (V16QI "b")
> - (V2DF "d")
> - (V4SF "w")])
> -
> ;; Map the Vector convert single precision to double precision for integer
> ;; versus floating point
> (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
> @@ -859,170 +838,6 @@ (define_insn "vs<SLDB_lr>db_<mode>"
> "vs<SLDB_lr>dbi %0,%1,%2,%3"
> [(set_attr "type" "vecsimple")])
>
> -(define_insn "xxspltiw_v4si"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> - "xxspltiw %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxspltiw_v4sf"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> -{
> - long value = rs6000_const_f32_to_i32 (operands[1]);
> - emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
> - DONE;
> -})
> -
> -(define_insn "xxspltiw_v4sf_inst"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> - "xxspltiw %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxspltidp_v2df"
> - [(set (match_operand:V2DF 0 "register_operand" )
> - (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
> - UNSPEC_XXSPLTID))]
> - "TARGET_POWER10"
> -{
> - long value = rs6000_const_f32_to_i32 (operands[1]);
> - rs6000_emit_xxspltidp_v2df (operands[0], value);
> - DONE;
> -})
> -
> -(define_insn "xxspltidp_v2df_inst"
> - [(set (match_operand:V2DF 0 "register_operand" "=wa")
> - (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTID))]
> - "TARGET_POWER10"
> - "xxspltidp %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxsplti32dx_v4si"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> -{
> - int index = INTVAL (operands[2]);
> -
> - if (!BYTES_BIG_ENDIAN)
> - index = 1 - index;
> -
> - emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
> - GEN_INT (index), operands[3]));
> - DONE;
> -}
> - [(set_attr "type" "vecsimple")])
> -
> -(define_insn "xxsplti32dx_v4si_inst"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> - "xxsplti32dx %x0,%2,%3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxsplti32dx_v4sf"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SF 3 "const_double_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> -{
> - int index = INTVAL (operands[2]);
> - long value = rs6000_const_f32_to_i32 (operands[3]);
> - if (!BYTES_BIG_ENDIAN)
> - index = 1 - index;
> -
> - emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
> - GEN_INT (index), GEN_INT (value)));
> - DONE;
> -})
> -
> -(define_insn "xxsplti32dx_v4sf_inst"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> - "xxsplti32dx %x0,%2,%3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_insn "xxblend_<mode>"
> - [(set (match_operand:VM3 0 "register_operand" "=wa")
> - (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
> - (match_operand:VM3 2 "register_operand" "wa")
> - (match_operand:VM3 3 "register_operand" "wa")]
> - UNSPEC_XXBLEND))]
> - "TARGET_POWER10"
> - "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxpermx"
> - [(set (match_operand:V2DI 0 "register_operand" "+wa")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> - (match_operand:V2DI 2 "register_operand" "wa")
> - (match_operand:V16QI 3 "register_operand" "wa")
> - (match_operand:QI 4 "u8bit_cint_operand" "n")]
> - UNSPEC_XXPERMX))]
> - "TARGET_POWER10"
> -{
> - if (BYTES_BIG_ENDIAN)
> - emit_insn (gen_xxpermx_inst (operands[0], operands[1],
> - operands[2], operands[3],
> - operands[4]));
> - else
> - {
> - /* Reverse value of byte element indexes by XORing with 0xFF.
> - Reverse the 32-byte section identifier match by subracting bits [0:2]
> - of elemet from 7. */
> - int value = INTVAL (operands[4]);
> - rtx vreg = gen_reg_rtx (V16QImode);
> -
> - emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
> - emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
> - value = 7 - value;
> - emit_insn (gen_xxpermx_inst (operands[0], operands[2],
> - operands[1], operands[3],
> - GEN_INT (value)));
> - }
> -
> - DONE;
> -}
> - [(set_attr "type" "vecsimple")])
> -
> -(define_insn "xxpermx_inst"
> - [(set (match_operand:V2DI 0 "register_operand" "+v")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
> - (match_operand:V2DI 2 "register_operand" "v")
> - (match_operand:V16QI 3 "register_operand" "v")
> - (match_operand:QI 4 "u3bit_cint_operand" "n")]
> - UNSPEC_XXPERMX))]
> - "TARGET_POWER10"
> - "xxpermx %x0,%x1,%x2,%x3,%4"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> (define_expand "vstrir_<mode>"
> [(set (match_operand:VIshort 0 "altivec_register_operand")
> (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
> @@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi"
> [(set_attr "type" "vecperm")
> (set_attr "isa" "p9v,*")])
>
> -(define_insn "xxeval"
> - [(set (match_operand:V2DI 0 "register_operand" "=wa")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> - (match_operand:V2DI 2 "register_operand" "wa")
> - (match_operand:V2DI 3 "register_operand" "wa")
> - (match_operand:QI 4 "u8bit_cint_operand" "n")]
> - UNSPEC_XXEVAL))]
> - "TARGET_POWER10"
> - "xxeval %0,%1,%2,%3,%4"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> (define_expand "vec_unpacku_hi_v16qi"
> [(set (match_operand:V8HI 0 "register_operand" "=v")
> (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 6f6fc0bd835..cacdd0d4cc8 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -372,6 +372,12 @@ (define_c_enum "unspec"
> UNSPEC_REPLACE_UN
> UNSPEC_VDIVES
> UNSPEC_VDIVEU
> + UNSPEC_XXEVAL
> + UNSPEC_XXSPLTIW
> + UNSPEC_XXSPLTID
> + UNSPEC_XXSPLTI32DX
> + UNSPEC_XXBLEND
> + UNSPEC_XXPERMX
> ])
>
> (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
> @@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2")
> (define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12")
> (V2DI "8") (V2DF "8")])
>
> +;; Like VM2 in altivec.md, just do char, short, int, long, float and double
> +(define_mode_iterator VM3 [V4SI
> + V8HI
> + V16QI
> + V4SF
> + V2DF
> + V2DI])
> +
> +(define_mode_attr VM3_char [(V2DI "d")
> + (V4SI "w")
> + (V8HI "h")
> + (V16QI "b")
> + (V2DF "d")
> + (V4SF "w")])
> +
> +
> ;; VSX moves
>
> ;; The patterns for LE permuted loads and stores come before the general
> @@ -6383,3 +6405,187 @@ (define_insn "mulv2di3"
> "TARGET_POWER10"
> "vmulld %0,%1,%2"
> [(set_attr "type" "veccomplex")])
> +
> +\f
> +;; XXSPLTIW built-in function support
> +(define_insn "xxspltiw_v4si"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> + "xxspltiw %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +(define_expand "xxspltiw_v4sf"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> +{
> + long value = rs6000_const_f32_to_i32 (operands[1]);
> + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
> + DONE;
> +})
> +
> +(define_insn "xxspltiw_v4sf_inst"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> + "xxspltiw %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXSPLTIDP built-in function support
> +(define_expand "xxspltidp_v2df"
> + [(set (match_operand:V2DF 0 "register_operand" )
> + (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
> + UNSPEC_XXSPLTID))]
> + "TARGET_POWER10"
> +{
> + long value = rs6000_const_f32_to_i32 (operands[1]);
> + rs6000_emit_xxspltidp_v2df (operands[0], value);
> + DONE;
> +})
> +
> +(define_insn "xxspltidp_v2df_inst"
> + [(set (match_operand:V2DF 0 "register_operand" "=wa")
> + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTID))]
> + "TARGET_POWER10"
> + "xxspltidp %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXSPLTI32DX built-in function support
> +(define_expand "xxsplti32dx_v4si"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> +{
> + int index = INTVAL (operands[2]);
> +
> + if (!BYTES_BIG_ENDIAN)
> + index = 1 - index;
> +
> + emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
> + GEN_INT (index), operands[3]));
> + DONE;
> +}
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "xxsplti32dx_v4si_inst"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> + "xxsplti32dx %x0,%2,%3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +(define_expand "xxsplti32dx_v4sf"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SF 3 "const_double_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> +{
> + int index = INTVAL (operands[2]);
> + long value = rs6000_const_f32_to_i32 (operands[3]);
> + if (!BYTES_BIG_ENDIAN)
> + index = 1 - index;
> +
> + emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
> + GEN_INT (index), GEN_INT (value)));
> + DONE;
> +})
> +
> +(define_insn "xxsplti32dx_v4sf_inst"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> + "xxsplti32dx %x0,%2,%3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXBLEND built-in function support
> +(define_insn "xxblend_<mode>"
> + [(set (match_operand:VM3 0 "register_operand" "=wa")
> + (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
> + (match_operand:VM3 2 "register_operand" "wa")
> + (match_operand:VM3 3 "register_operand" "wa")]
> + UNSPEC_XXBLEND))]
> + "TARGET_POWER10"
> + "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXPERMX built-in function support
> +(define_expand "xxpermx"
> + [(set (match_operand:V2DI 0 "register_operand" "+wa")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> + (match_operand:V2DI 2 "register_operand" "wa")
> + (match_operand:V16QI 3 "register_operand" "wa")
> + (match_operand:QI 4 "u8bit_cint_operand" "n")]
> + UNSPEC_XXPERMX))]
> + "TARGET_POWER10"
> +{
> + if (BYTES_BIG_ENDIAN)
> + emit_insn (gen_xxpermx_inst (operands[0], operands[1],
> + operands[2], operands[3],
> + operands[4]));
> + else
> + {
> + /* Reverse value of byte element indexes by XORing with 0xFF.
> + Reverse the 32-byte section identifier match by subracting bits [0:2]
> + of elemet from 7. */
> + int value = INTVAL (operands[4]);
> + rtx vreg = gen_reg_rtx (V16QImode);
> +
> + emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
> + emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
> + value = 7 - value;
> + emit_insn (gen_xxpermx_inst (operands[0], operands[2],
> + operands[1], operands[3],
> + GEN_INT (value)));
> + }
> +
> + DONE;
> +}
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "xxpermx_inst"
> + [(set (match_operand:V2DI 0 "register_operand" "+v")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
> + (match_operand:V2DI 2 "register_operand" "v")
> + (match_operand:V16QI 3 "register_operand" "v")
> + (match_operand:QI 4 "u3bit_cint_operand" "n")]
> + UNSPEC_XXPERMX))]
> + "TARGET_POWER10"
> + "xxpermx %x0,%x1,%x2,%x3,%4"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXEVAL built-in function support
> +(define_insn "xxeval"
> + [(set (match_operand:V2DI 0 "register_operand" "=wa")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> + (match_operand:V2DI 2 "register_operand" "wa")
> + (match_operand:V2DI 3 "register_operand" "wa")
> + (match_operand:QI 4 "u8bit_cint_operand" "n")]
> + UNSPEC_XXEVAL))]
> + "TARGET_POWER10"
> + "xxeval %0,%1,%2,%3,%4"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> --
> 2.31.1
> ---
> gcc/config/rs6000/altivec.md | 197 ---------------------------------
> gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++
> 2 files changed, 206 insertions(+), 197 deletions(-)
>
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index fd86c300981..2c73ddea823 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -175,16 +175,10 @@ (define_c_enum "unspec"
> UNSPEC_VPEXTD
> UNSPEC_VCLRLB
> UNSPEC_VCLRRB
> - UNSPEC_XXEVAL
> UNSPEC_VSTRIR
> UNSPEC_VSTRIL
> UNSPEC_SLDB
> UNSPEC_SRDB
> - UNSPEC_XXSPLTIW
> - UNSPEC_XXSPLTID
> - UNSPEC_XXSPLTI32DX
> - UNSPEC_XXBLEND
> - UNSPEC_XXPERMX
> ])
>
> (define_c_enum "unspecv"
> @@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI
> (KF "FLOAT128_VECTOR_P (KFmode)")
> (TF "FLOAT128_VECTOR_P (TFmode)")])
>
> -;; Like VM2, just do char, short, int, long, float and double
> -(define_mode_iterator VM3 [V4SI
> - V8HI
> - V16QI
> - V4SF
> - V2DF
> - V2DI])
> -
> -(define_mode_attr VM3_char [(V2DI "d")
> - (V4SI "w")
> - (V8HI "h")
> - (V16QI "b")
> - (V2DF "d")
> - (V4SF "w")])
> -
> ;; Map the Vector convert single precision to double precision for integer
> ;; versus floating point
> (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
> @@ -859,170 +838,6 @@ (define_insn "vs<SLDB_lr>db_<mode>"
> "vs<SLDB_lr>dbi %0,%1,%2,%3"
> [(set_attr "type" "vecsimple")])
>
> -(define_insn "xxspltiw_v4si"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> - "xxspltiw %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxspltiw_v4sf"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> -{
> - long value = rs6000_const_f32_to_i32 (operands[1]);
> - emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
> - DONE;
> -})
> -
> -(define_insn "xxspltiw_v4sf_inst"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTIW))]
> - "TARGET_POWER10"
> - "xxspltiw %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxspltidp_v2df"
> - [(set (match_operand:V2DF 0 "register_operand" )
> - (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
> - UNSPEC_XXSPLTID))]
> - "TARGET_POWER10"
> -{
> - long value = rs6000_const_f32_to_i32 (operands[1]);
> - rs6000_emit_xxspltidp_v2df (operands[0], value);
> - DONE;
> -})
> -
> -(define_insn "xxspltidp_v2df_inst"
> - [(set (match_operand:V2DF 0 "register_operand" "=wa")
> - (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTID))]
> - "TARGET_POWER10"
> - "xxspltidp %x0,%1"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxsplti32dx_v4si"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> -{
> - int index = INTVAL (operands[2]);
> -
> - if (!BYTES_BIG_ENDIAN)
> - index = 1 - index;
> -
> - emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
> - GEN_INT (index), operands[3]));
> - DONE;
> -}
> - [(set_attr "type" "vecsimple")])
> -
> -(define_insn "xxsplti32dx_v4si_inst"
> - [(set (match_operand:V4SI 0 "register_operand" "=wa")
> - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> - "xxsplti32dx %x0,%2,%3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxsplti32dx_v4sf"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SF 3 "const_double_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> -{
> - int index = INTVAL (operands[2]);
> - long value = rs6000_const_f32_to_i32 (operands[3]);
> - if (!BYTES_BIG_ENDIAN)
> - index = 1 - index;
> -
> - emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
> - GEN_INT (index), GEN_INT (value)));
> - DONE;
> -})
> -
> -(define_insn "xxsplti32dx_v4sf_inst"
> - [(set (match_operand:V4SF 0 "register_operand" "=wa")
> - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> - (match_operand:QI 2 "u1bit_cint_operand" "n")
> - (match_operand:SI 3 "s32bit_cint_operand" "n")]
> - UNSPEC_XXSPLTI32DX))]
> - "TARGET_POWER10"
> - "xxsplti32dx %x0,%2,%3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_insn "xxblend_<mode>"
> - [(set (match_operand:VM3 0 "register_operand" "=wa")
> - (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
> - (match_operand:VM3 2 "register_operand" "wa")
> - (match_operand:VM3 3 "register_operand" "wa")]
> - UNSPEC_XXBLEND))]
> - "TARGET_POWER10"
> - "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> -(define_expand "xxpermx"
> - [(set (match_operand:V2DI 0 "register_operand" "+wa")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> - (match_operand:V2DI 2 "register_operand" "wa")
> - (match_operand:V16QI 3 "register_operand" "wa")
> - (match_operand:QI 4 "u8bit_cint_operand" "n")]
> - UNSPEC_XXPERMX))]
> - "TARGET_POWER10"
> -{
> - if (BYTES_BIG_ENDIAN)
> - emit_insn (gen_xxpermx_inst (operands[0], operands[1],
> - operands[2], operands[3],
> - operands[4]));
> - else
> - {
> - /* Reverse value of byte element indexes by XORing with 0xFF.
> - Reverse the 32-byte section identifier match by subracting bits [0:2]
> - of elemet from 7. */
> - int value = INTVAL (operands[4]);
> - rtx vreg = gen_reg_rtx (V16QImode);
> -
> - emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
> - emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
> - value = 7 - value;
> - emit_insn (gen_xxpermx_inst (operands[0], operands[2],
> - operands[1], operands[3],
> - GEN_INT (value)));
> - }
> -
> - DONE;
> -}
> - [(set_attr "type" "vecsimple")])
> -
> -(define_insn "xxpermx_inst"
> - [(set (match_operand:V2DI 0 "register_operand" "+v")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
> - (match_operand:V2DI 2 "register_operand" "v")
> - (match_operand:V16QI 3 "register_operand" "v")
> - (match_operand:QI 4 "u3bit_cint_operand" "n")]
> - UNSPEC_XXPERMX))]
> - "TARGET_POWER10"
> - "xxpermx %x0,%x1,%x2,%x3,%4"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> (define_expand "vstrir_<mode>"
> [(set (match_operand:VIshort 0 "altivec_register_operand")
> (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
> @@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi"
> [(set_attr "type" "vecperm")
> (set_attr "isa" "p9v,*")])
>
> -(define_insn "xxeval"
> - [(set (match_operand:V2DI 0 "register_operand" "=wa")
> - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> - (match_operand:V2DI 2 "register_operand" "wa")
> - (match_operand:V2DI 3 "register_operand" "wa")
> - (match_operand:QI 4 "u8bit_cint_operand" "n")]
> - UNSPEC_XXEVAL))]
> - "TARGET_POWER10"
> - "xxeval %0,%1,%2,%3,%4"
> - [(set_attr "type" "vecsimple")
> - (set_attr "prefixed" "yes")])
> -
> (define_expand "vec_unpacku_hi_v16qi"
> [(set (match_operand:V8HI 0 "register_operand" "=v")
> (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 441735df9c3..e4ca6e94d49 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -372,6 +372,12 @@ (define_c_enum "unspec"
> UNSPEC_REPLACE_UN
> UNSPEC_VDIVES
> UNSPEC_VDIVEU
> + UNSPEC_XXEVAL
> + UNSPEC_XXSPLTIW
> + UNSPEC_XXSPLTID
> + UNSPEC_XXSPLTI32DX
> + UNSPEC_XXBLEND
> + UNSPEC_XXPERMX
> ])
>
> (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
> @@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2")
> (define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12")
> (V2DI "8") (V2DF "8")])
>
> +;; Like VM2 in altivec.md, just do char, short, int, long, float and double
> +(define_mode_iterator VM3 [V4SI
> + V8HI
> + V16QI
> + V4SF
> + V2DF
> + V2DI])
> +
> +(define_mode_attr VM3_char [(V2DI "d")
> + (V4SI "w")
> + (V8HI "h")
> + (V16QI "b")
> + (V2DF "d")
> + (V4SF "w")])
> +
> +
> ;; VSX moves
>
> ;; The patterns for LE permuted loads and stores come before the general
> @@ -6383,3 +6405,187 @@ (define_insn "mulv2di3"
> "TARGET_POWER10"
> "vmulld %0,%1,%2"
> [(set_attr "type" "veccomplex")])
> +
> +\f
> +;; XXSPLTIW built-in function support
> +(define_insn "xxspltiw_v4si"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> + "xxspltiw %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +(define_expand "xxspltiw_v4sf"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> +{
> + long value = rs6000_const_f32_to_i32 (operands[1]);
> + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
> + DONE;
> +})
> +
> +(define_insn "xxspltiw_v4sf_inst"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTIW))]
> + "TARGET_POWER10"
> + "xxspltiw %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXSPLTIDP built-in function support
> +(define_expand "xxspltidp_v2df"
> + [(set (match_operand:V2DF 0 "register_operand" )
> + (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
> + UNSPEC_XXSPLTID))]
> + "TARGET_POWER10"
> +{
> + long value = rs6000_const_f32_to_i32 (operands[1]);
> + rs6000_emit_xxspltidp_v2df (operands[0], value);
> + DONE;
> +})
> +
> +(define_insn "xxspltidp_v2df_inst"
> + [(set (match_operand:V2DF 0 "register_operand" "=wa")
> + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTID))]
> + "TARGET_POWER10"
> + "xxspltidp %x0,%1"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXSPLTI32DX built-in function support
> +(define_expand "xxsplti32dx_v4si"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> +{
> + int index = INTVAL (operands[2]);
> +
> + if (!BYTES_BIG_ENDIAN)
> + index = 1 - index;
> +
> + emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
> + GEN_INT (index), operands[3]));
> + DONE;
> +}
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "xxsplti32dx_v4si_inst"
> + [(set (match_operand:V4SI 0 "register_operand" "=wa")
> + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> + "xxsplti32dx %x0,%2,%3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +(define_expand "xxsplti32dx_v4sf"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SF 3 "const_double_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> +{
> + int index = INTVAL (operands[2]);
> + long value = rs6000_const_f32_to_i32 (operands[3]);
> + if (!BYTES_BIG_ENDIAN)
> + index = 1 - index;
> +
> + emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
> + GEN_INT (index), GEN_INT (value)));
> + DONE;
> +})
> +
> +(define_insn "xxsplti32dx_v4sf_inst"
> + [(set (match_operand:V4SF 0 "register_operand" "=wa")
> + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
> + (match_operand:QI 2 "u1bit_cint_operand" "n")
> + (match_operand:SI 3 "s32bit_cint_operand" "n")]
> + UNSPEC_XXSPLTI32DX))]
> + "TARGET_POWER10"
> + "xxsplti32dx %x0,%2,%3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXBLEND built-in function support
> +(define_insn "xxblend_<mode>"
> + [(set (match_operand:VM3 0 "register_operand" "=wa")
> + (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
> + (match_operand:VM3 2 "register_operand" "wa")
> + (match_operand:VM3 3 "register_operand" "wa")]
> + UNSPEC_XXBLEND))]
> + "TARGET_POWER10"
> + "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXPERMX built-in function support
> +(define_expand "xxpermx"
> + [(set (match_operand:V2DI 0 "register_operand" "+wa")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> + (match_operand:V2DI 2 "register_operand" "wa")
> + (match_operand:V16QI 3 "register_operand" "wa")
> + (match_operand:QI 4 "u8bit_cint_operand" "n")]
> + UNSPEC_XXPERMX))]
> + "TARGET_POWER10"
> +{
> + if (BYTES_BIG_ENDIAN)
> + emit_insn (gen_xxpermx_inst (operands[0], operands[1],
> + operands[2], operands[3],
> + operands[4]));
> + else
> + {
> + /* Reverse value of byte element indexes by XORing with 0xFF.
> + Reverse the 32-byte section identifier match by subracting bits [0:2]
> + of elemet from 7. */
> + int value = INTVAL (operands[4]);
> + rtx vreg = gen_reg_rtx (V16QImode);
> +
> + emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
> + emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
> + value = 7 - value;
> + emit_insn (gen_xxpermx_inst (operands[0], operands[2],
> + operands[1], operands[3],
> + GEN_INT (value)));
> + }
> +
> + DONE;
> +}
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "xxpermx_inst"
> + [(set (match_operand:V2DI 0 "register_operand" "+v")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
> + (match_operand:V2DI 2 "register_operand" "v")
> + (match_operand:V16QI 3 "register_operand" "v")
> + (match_operand:QI 4 "u3bit_cint_operand" "n")]
> + UNSPEC_XXPERMX))]
> + "TARGET_POWER10"
> + "xxpermx %x0,%x1,%x2,%x3,%4"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
> +;; XXEVAL built-in function support
> +(define_insn "xxeval"
> + [(set (match_operand:V2DI 0 "register_operand" "=wa")
> + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> + (match_operand:V2DI 2 "register_operand" "wa")
> + (match_operand:V2DI 3 "register_operand" "wa")
> + (match_operand:QI 4 "u8bit_cint_operand" "n")]
> + UNSPEC_XXEVAL))]
> + "TARGET_POWER10"
> + "xxeval %0,%1,%2,%3,%4"
> + [(set_attr "type" "vecsimple")
> + (set_attr "prefixed" "yes")])
> +
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Move xx* builtins to vsx.md.
2021-08-13 4:20 [PATCH] Move xx* builtins to vsx.md Michael Meissner
2021-08-18 20:01 ` Bill Schmidt
@ 2021-08-18 20:42 ` David Edelsohn
2021-08-18 23:11 ` Segher Boessenkool
1 sibling, 1 reply; 6+ messages in thread
From: David Edelsohn @ 2021-08-18 20:42 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, Segher Boessenkool,
David Edelsohn, Bill Schmidt, Peter Bergner, Will Schmidt
On Fri, Aug 13, 2021 at 12:20 AM Michael Meissner
<meissner@linux.ibm.com> wrote:
>
> Move xx* builtins to vsx.md.
>
> I originally posted this patch in May. It needed a slight tune up as the
> souces have changed, so I'm reposting it now.
>
> I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
> xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since
> the XX instructions can take both traditional floating point and Altivec
> registers, these built-in functions should be in vsx.md.
>
> This patch just moves the insns from altivec.md to vsx.md.
>
> I also moved the VM3 mode iterator and VM3_char mode attribute from altivec.md
> to vsx.md, since the only use of these were for the XXBLEND insns.
>
> I have built little endian power9 compilers, little endian power10 compilers,
> and big endian power8 compilers with this patch applied, and there were no
> regressions. Can I apply this patch to the master branch?
>
> Note this patch assumes the previous patch:
>
> Fix xxeval predicates (PR 99921).
>
> has been applied.
>
> 2021-08-12 Michael Meissner <meissner@linux.ibm.com>
>
> gcc/
> * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
> (UNSPEC_XXSPLTIW): Move to vsx.md.
> (UNSPEC_XXSPLTID): Move to vsx.md.
> (UNSPEC_XXSPLTI32DX): Move to vsx.md.
> (UNSPEC_XXBLEND): Move to vsx.md.
> (UNSPEC_XXPERMX): Move to vsx.md.
> (VM3): Move to vsx.md.
> (VM3_char): Move to vsx.md.
> (xxspltiw_v4si): Move to vsx.md.
> (xxspltiw_v4sf): Move to vsx.md.
> (xxspltiw_v4sf_inst): Move to vsx.md.
> (xxspltidp_v2df): Move to vsx.md.
> (xxspltidp_v2df_inst): Move to vsx.md.
> (xxsplti32dx_v4si_inst): Move to vsx.md.
> (xxsplti32dx_v4sf): Move to vsx.md.
> (xxsplti32dx_v4sf_inst): Move to vsx.md.
> (xxblend_<mode>): Move to vsx.md.
> (xxpermx): Move to vsx.md.
> (xxpermx_inst): Move to vsx.md.
> * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
> (UNSPEC_XXSPLTIW): Move from altivec.md.
> (UNSPEC_XXSPLTID): Move from altivec.md.
> (UNSPEC_XXSPLTI32DX): Move from altivec.md.
> (UNSPEC_XXBLEND): Move from altivec.md.
> (UNSPEC_XXPERMX): Move from altivec.md.
> (VM3): Move from altivec.md.
> (VM3_char): Move from altivec.md.
> (xxspltiw_v4si): Move from altivec.md.
> (xxspltiw_v4sf): Move from altivec.md.
> (xxspltiw_v4sf_inst): Move from altivec.md.
> (xxspltidp_v2df): Move from altivec.md.
> (xxspltidp_v2df_inst): Move from altivec.md.
> (xxsplti32dx_v4si_inst): Move from altivec.md.
> (xxsplti32dx_v4sf): Move from altivec.md.
> (xxsplti32dx_v4sf_inst): Move from altivec.md.
> (xxblend_<mode>): Move from altivec.md.
> (xxpermx): Move from altivec.md.
> (xxpermx_inst): Move from altivec.md
Okay.
I wanted to give Segher a chance to comment on the structure.
You could have used "Same" or "Likewise" in the ChangeLog, but that's fine.
Thanks, David
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Move xx* builtins to vsx.md.
2021-08-18 20:42 ` David Edelsohn
@ 2021-08-18 23:11 ` Segher Boessenkool
2021-08-19 22:10 ` Michael Meissner
0 siblings, 1 reply; 6+ messages in thread
From: Segher Boessenkool @ 2021-08-18 23:11 UTC (permalink / raw)
To: David Edelsohn
Cc: Michael Meissner, GCC Patches, Bill Schmidt, Peter Bergner, Will Schmidt
On Wed, Aug 18, 2021 at 04:42:42PM -0400, David Edelsohn wrote:
> I wanted to give Segher a chance to comment on the structure.
I think the current vector.md / altivec.md / vsx.md / rs6000.md
division is artificial at best. Most of the basic (movement etc.)
things are in rs6000.md (and all should be), but nothing else is clear.
The name "altivec.md" suggests it is only for the very old things, but
it is not used that way, and that it untenable anyway: we have more
recent insns to plug holes in that (for example 64-bit integer support),
so it arguably is not just for that.
Using it for instructions that only work on the high 32 VSRs (i.e. the
VRs) is quite artificial as well -- sometimes there are equivalent insns
for the other 32 VSRs already, sometimes it is just because of opcode
scarcity, sometimes it is because it is for the slow vector unit only
(but those seem to live in rs6000.md and crypto.md anyway).
Maybe we should give up on dividing these things, and put both in one
file, say vector.md?
Segher
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Move xx* builtins to vsx.md.
2021-08-18 23:11 ` Segher Boessenkool
@ 2021-08-19 22:10 ` Michael Meissner
2021-08-19 22:18 ` Segher Boessenkool
0 siblings, 1 reply; 6+ messages in thread
From: Michael Meissner @ 2021-08-19 22:10 UTC (permalink / raw)
To: Segher Boessenkool
Cc: David Edelsohn, Michael Meissner, GCC Patches, Bill Schmidt,
Peter Bergner, Will Schmidt
On Wed, Aug 18, 2021 at 06:11:03PM -0500, Segher Boessenkool wrote:
> On Wed, Aug 18, 2021 at 04:42:42PM -0400, David Edelsohn wrote:
> > I wanted to give Segher a chance to comment on the structure.
>
> I think the current vector.md / altivec.md / vsx.md / rs6000.md
> division is artificial at best. Most of the basic (movement etc.)
> things are in rs6000.md (and all should be), but nothing else is clear.
>
> The name "altivec.md" suggests it is only for the very old things, but
> it is not used that way, and that it untenable anyway: we have more
> recent insns to plug holes in that (for example 64-bit integer support),
> so it arguably is not just for that.
>
> Using it for instructions that only work on the high 32 VSRs (i.e. the
> VRs) is quite artificial as well -- sometimes there are equivalent insns
> for the other 32 VSRs already, sometimes it is just because of opcode
> scarcity, sometimes it is because it is for the slow vector unit only
> (but those seem to live in rs6000.md and crypto.md anyway).
>
> Maybe we should give up on dividing these things, and put both in one
> file, say vector.md?
Yes but that is more ambitious. Basically I have 2 patches coming that use and
update the xxsplti instructions. I can avoid putting in this specific change
and reformulate them for altivec.md instead of vsx.md. Or I can check in these
changes. Which do you want? I don't want to do both insn movement and new
patches at the same time.
The original design of vector.md was to allow for alternate vector units, and
vector.md was just the define_expands. But the likely hood of new vector units
is probably low.
When I wrote vsx.md in the power7 days, we were toying with the notion of doing
VSX and not Altivec instructions. But I quickly realized you always need
Altivec for VSX.
In general, I would prefer not to have a flag day where everything gets moved
all at once.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Move xx* builtins to vsx.md.
2021-08-19 22:10 ` Michael Meissner
@ 2021-08-19 22:18 ` Segher Boessenkool
0 siblings, 0 replies; 6+ messages in thread
From: Segher Boessenkool @ 2021-08-19 22:18 UTC (permalink / raw)
To: Michael Meissner, David Edelsohn, GCC Patches, Bill Schmidt,
Peter Bergner, Will Schmidt
On Thu, Aug 19, 2021 at 06:10:46PM -0400, Michael Meissner wrote:
> On Wed, Aug 18, 2021 at 06:11:03PM -0500, Segher Boessenkool wrote:
> > I think the current vector.md / altivec.md / vsx.md / rs6000.md
> > division is artificial at best. Most of the basic (movement etc.)
> > things are in rs6000.md (and all should be), but nothing else is clear.
> >
> > The name "altivec.md" suggests it is only for the very old things, but
> > it is not used that way, and that it untenable anyway: we have more
> > recent insns to plug holes in that (for example 64-bit integer support),
> > so it arguably is not just for that.
> >
> > Using it for instructions that only work on the high 32 VSRs (i.e. the
> > VRs) is quite artificial as well -- sometimes there are equivalent insns
> > for the other 32 VSRs already, sometimes it is just because of opcode
> > scarcity, sometimes it is because it is for the slow vector unit only
> > (but those seem to live in rs6000.md and crypto.md anyway).
> >
> > Maybe we should give up on dividing these things, and put both in one
> > file, say vector.md?
>
> Yes but that is more ambitious.
Absolutely. But setting a destination before starting to walk is
sometimes helpful ;-)
> Basically I have 2 patches coming that use and
> update the xxsplti instructions. I can avoid putting in this specific change
> and reformulate them for altivec.md instead of vsx.md. Or I can check in these
> changes. Which do you want? I don't want to do both insn movement and new
> patches at the same time.
I am fine with this patch, it is a clear improvement already.
> The original design of vector.md was to allow for alternate vector units, and
> vector.md was just the define_expands. But the likely hood of new vector units
> is probably low.
Right, history has caught up with us.
> When I wrote vsx.md in the power7 days, we were toying with the notion of doing
> VSX and not Altivec instructions. But I quickly realized you always need
> Altivec for VSX.
There also were 8-byte vectors back then. Or was that completely
separate code?
> In general, I would prefer not to have a flag day where everything gets moved
> all at once.
Yup, it is too easy to make mistakes here, ordering in machine
descriptions is significant. Although comparing the generated insn-*
files before and after might help.
Segher
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-08-19 22:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-13 4:20 [PATCH] Move xx* builtins to vsx.md Michael Meissner
2021-08-18 20:01 ` Bill Schmidt
2021-08-18 20:42 ` David Edelsohn
2021-08-18 23:11 ` Segher Boessenkool
2021-08-19 22:10 ` Michael Meissner
2021-08-19 22:18 ` Segher Boessenkool
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