From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id EF2833857829 for ; Mon, 14 Mar 2022 11:25:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF2833857829 Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-523--NwbWVJGNNe-JBwe8Sh_hw-1; Mon, 14 Mar 2022 07:25:26 -0400 X-MC-Unique: -NwbWVJGNNe-JBwe8Sh_hw-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EA0273C1EA40; Mon, 14 Mar 2022 11:25:25 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.81]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AAD3E1466C66; Mon, 14 Mar 2022 11:25:25 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 22EBPMgX300831 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 14 Mar 2022 12:25:23 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 22EBPMhj300830; Mon, 14 Mar 2022 12:25:22 +0100 Date: Mon, 14 Mar 2022 12:25:22 +0100 From: Jakub Jelinek To: Hongtao Liu Cc: Uros Bizjak , GCC Patches , "H. J. Lu" Subject: Re: [PATCH] i386: Fix up _mm_loadu_si{16,32} [PR99754] Message-ID: Reply-To: Jakub Jelinek References: MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.85 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Mar 2022 11:25:30 -0000 On Sun, Mar 13, 2022 at 09:34:10PM +0800, Hongtao Liu wrote: > LGTM, thanks for handling this. Thanks, committed. > > Note, while the Intrinsics guide for _mm_loadu_si32 says SSE2, > > for _mm_loadu_si16 it says strangely SSE. But the intrinsics > > returns __m128i, which is only defined in emmintrin.h, and > > _mm_set_epi16 is also only SSE2 and later in emmintrin.h. > > Even clang defines it in emmintrin.h and ends up with inlining > > failure when calling _mm_loadu_si16 from sse,no-sse2 function. > > So, isn't that a bug in the intrinsic guide instead? > I think it's a bug, it's supposed to generate movzx + movd, and movd > is under sse2, and have reported it to the colleague who maintains > Intel intrinsic guide. > > Similar bug for > _mm_loadu_si64 > _mm_storeu_si16 > _mm_storeu_si64 Currently it emits pxor + pinsrw, but even those are SSE2 instructions, unless they use a MMX register (then it is MMX and SSE). I agree that movzwl + movd seems better than pxor + pinsrw though. So, do we want to help it a little bit then? Like: 2022-03-14 Jakub Jelinek * config/i386/eemintrin.h (_mm_loadu_si16): Use _mm_set_epi32 instead of _mm_set_epi16 and zero extend the memory load. * gcc.target/i386/pr95483-1.c: Use -msse2 instead of -msse in dg-options, allow movzwl+movd instead of pxor with pinsrw. --- gcc/config/i386/emmintrin.h.jj 2022-03-14 10:44:29.402617685 +0100 +++ gcc/config/i386/emmintrin.h 2022-03-14 11:58:18.062666257 +0100 @@ -724,7 +724,7 @@ _mm_loadu_si32 (void const *__P) extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_loadu_si16 (void const *__P) { - return _mm_set_epi16 (0, 0, 0, 0, 0, 0, 0, (*(__m16_u *)__P)[0]); + return _mm_set_epi32 (0, 0, 0, (unsigned short) ((*(__m16_u *)__P)[0])); } extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) --- gcc/testsuite/gcc.target/i386/pr95483-1.c.jj 2020-10-14 22:05:19.380856952 +0200 +++ gcc/testsuite/gcc.target/i386/pr95483-1.c 2022-03-14 12:11:07.716891710 +0100 @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse" } */ -/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "pinsrw\[ \\t\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-final { scan-assembler-times "(?:movzwl\[ \\t\]+\[^\n\]*|pxor\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+)(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "(?:movd|pinsrw)\[ \\t\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "pextrw\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*(?:\n|\[ \\t\]+#)" 1 } } */ Jakub