From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 63D943858D1E for ; Sat, 5 Mar 2022 08:05:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 63D943858D1E Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-30-KyUFLjT3NAqa3S74BUQQbQ-1; Sat, 05 Mar 2022 03:05:27 -0500 X-MC-Unique: KyUFLjT3NAqa3S74BUQQbQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4BC23801AAD; Sat, 5 Mar 2022 08:05:26 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.81]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D70FE1F473; Sat, 5 Mar 2022 08:05:25 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 22585N5f2772039 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sat, 5 Mar 2022 09:05:23 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 22585MGY2772038; Sat, 5 Mar 2022 09:05:22 +0100 Date: Sat, 5 Mar 2022 09:05:22 +0100 From: Jakub Jelinek To: Hongtao Liu , Uros Bizjak Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] i386: Fix up cond_{and,ior,xor,mul}* [PR104779] Message-ID: Reply-To: Jakub Jelinek MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Mar 2022 08:05:34 -0000 Hi! The following testcase ICEs, because the cond_andv* expander has vector_operand predicates in both of the commutative inputs and calls gen_andv*_mask which calls ix86_binary_operator_ok in its condition, but nothing calls ix86_fixup_binary_operands_no_copy during the expansion, which means cond_* accepts even operands like 2 MEMs which then can't be matched. The following patch handles it like most other insns that the other cond_* patterns use - by having a separate define_expand that calls ix86_fixup_binary_operands_no_copy and define_ins with ix86_binary_operator_ok. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Note, the predicates on cond_fma* and other FMA variants look all wrong to me, usually the fma instructions require nonimmediate_operand operands, but the cond_* patterns use vector_operand. Besides what this patch fixes and the unfixed fma which I don't have spare cycles for right now I went through all the other cond_* patterns checking for predicate mismatches or similar missing ix86_fixup_binary_operands* issues and didn't find other problems. 2022-03-05 Jakub Jelinek PR target/104779 * config/i386/sse.md (avx512dq_mul3): New define_expand pattern. Rename define_insn to ... (*avx512dq_mul3): ... this. (3_mask): New any_logic define_expand pattern. (3): Rename to ... (*3): ... this. * gcc.target/i386/pr104779.c: New test. --- gcc/config/i386/sse.md.jj 2022-02-24 15:27:14.722743984 +0100 +++ gcc/config/i386/sse.md 2022-03-04 13:56:34.863572916 +0100 @@ -15210,7 +15210,15 @@ (define_expand "cond_mul" DONE; }) -(define_insn "avx512dq_mul3" +(define_expand "avx512dq_mul3" + [(set (match_operand:VI8_AVX512VL 0 "register_operand") + (mult:VI8_AVX512VL + (match_operand:VI8_AVX512VL 1 "bcst_vector_operand") + (match_operand:VI8_AVX512VL 2 "bcst_vector_operand")))] + "TARGET_AVX512DQ && " + "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);") + +(define_insn "*avx512dq_mul3" [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") (mult:VI8_AVX512VL (match_operand:VI8_AVX512VL 1 "bcst_vector_operand" "%v") @@ -16824,7 +16832,18 @@ (define_expand "cond_" DONE; }) -(define_insn "3" +(define_expand "3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (any_logic:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "bcst_vector_operand") + (match_operand:VI48_AVX512VL 2 "bcst_vector_operand")) + (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512F" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*3" [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v") (any_logic:VI48_AVX_AVX512F (match_operand:VI48_AVX_AVX512F 1 "bcst_vector_operand" "%0,x,v") --- gcc/testsuite/gcc.target/i386/pr104779.c.jj 2022-03-04 14:09:03.278961269 +0100 +++ gcc/testsuite/gcc.target/i386/pr104779.c 2022-03-04 14:08:38.063318794 +0100 @@ -0,0 +1,27 @@ +/* PR target/104779 */ +/* { dg-do compile } */ +/* { dg-options "-O1 --param sccvn-max-alias-queries-per-access=0" } */ + +__attribute__ ((simd)) int +foo (int x, int y, int z) +{ + return (x & y) * !!z; +} + +__attribute__ ((simd)) int +bar (int x, int y, int z) +{ + return (x | y) * !!z; +} + +__attribute__ ((simd)) int +baz (int x, int y, int z) +{ + return (x ^ y) * !!z; +} + +__attribute__ ((simd, target ("avx512dq"))) long +qux (long x, long y, long z) +{ + return (x * y) * !!z; +} Jakub