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From: Michael Meissner <meissner@linux.ibm.com>
To: Michael Meissner <meissner@linux.ibm.com>,
	gcc-patches@gcc.gnu.org,
	Segher Boessenkool <segher@kernel.crashing.org>,
	David Edelsohn <dje.gcc@gmail.com>,
	Peter Bergner <bergner@linux.ibm.com>,
	Will Schmidt <will_schmidt@vnet.ibm.com>
Subject: [PATCH 3/4] Make vsx_extract_<mode> use correct insn attributes, PR target 99293.
Date: Mon, 28 Mar 2022 12:28:04 -0400	[thread overview]
Message-ID: <YkHiFLLuHIS4R59K@toto.the-meissners.org> (raw)
In-Reply-To: <YkHhL5rL39UoKIHC@toto.the-meissners.org>

Make vsx_extract_<mode> use correct insn attributes, PR target 99293.

In looking at PR target/99293, I noticed that the insn "type" attribute is
incorrect for the vsx_extract_<mode> insns.  In particular:

    1)	Simple vector register move should be vecmove (alternative 1);
    2)	Xxpermdi should be vecperm (alternative 2); (and)
    3)	Mfvsrld should be mfvsr (alternative 4).

This patch fixes those attributes.

I have built the spec 2017 benchmark with this patch (#3) and the previous
patch (#2), along with the first patch in the series for power9 and
power10 targets.  Most of the floating point benchmarks changed code
slightly, due to the scheduling changes that came from changing the insn
type attribute.  I ran the spec 2017 suite on power9, and I did not not
notice any significant changes from these changes.

The power9 benchmarks that had code differences with these 2 patches
applied in addition to the build with just the first patch applied were:

	namd_r, pareset_r, povray_r, wrf_r, blender_r, cam4_r,
	deepsjeng_r, imagick_r, roms_r

The power9 benchmarks that had code differences with these 2 patches
applied in addition to the build with just the first patch applied were
(cactuBSSN_r had changes for power10 but not power9):

	cactuBSSN_r, namd_r, pareset_r, povray_r, wrf_r, blender_r,
	cam4_r, deepsjeng_r, imagick_r, nab_r, roms_r

I have built bootstrap versions on the following systems.  There were no
regressions in the runs:

	Power9 little endian, --with-cpu=power9
	Power10 little endian, --with-cpu=power10
	Power8 big endian, --with-cpu=power8 (both 32-bit & 64-bit tests)

Can I install this into the trunk?  After a burn-in period, can I backport
and install this into GCC 11 and GCC 10 branches?

2022-03-28   Michael Meissner  <meissner@linux.ibm.com>

gcc/
	PR target/99293
	* config/rs6000/rs6000.md (vsx_extract_<mode>): Use the correct
	insn type for the alternatives.
---
 gcc/config/rs6000/vsx.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ad722cff70f..2a23807c2dc 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3451,7 +3451,7 @@ (define_insn "vsx_extract_<mode>"
   else
     gcc_unreachable ();
 }
-  [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm")
+  [(set_attr "type" "vecmove,vecperm,mfvsr,mfvsr")
    (set_attr "isa" "*,*,p8v,p9v")])
 
 ;; Optimize extracting a single scalar element from memory.
-- 
2.35.1


-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com

  parent reply	other threads:[~2022-03-28 16:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-28 16:24 [PATCH 0/4] Optimize vec_splats of vec_extract, PR target/99293 Michael Meissner
2022-03-28 16:26 ` [PATCH 1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293 Michael Meissner
2022-03-28 17:14   ` Segher Boessenkool
2022-03-28 22:30     ` Michael Meissner
2022-03-28 23:25       ` Segher Boessenkool
2022-03-28 16:27 ` [PATCH 2/4] Make vsx_splat_<mode>_reg use correct insn attributes, PR target/99293 Michael Meissner
2022-03-28 20:28   ` Segher Boessenkool
2022-03-30 22:41     ` Michael Meissner
2022-04-01 17:21       ` Segher Boessenkool
2022-03-28 16:28 ` Michael Meissner [this message]
2022-03-28 22:06   ` [PATCH 3/4] Make vsx_extract_<mode> use correct insn attributes, PR target 99293 Segher Boessenkool
2022-03-30 22:58     ` Michael Meissner
2022-03-28 16:28 ` [PATCH 4/4] Allow vsx_extract_<mode> to use Altivec registers, PR target/99293 Michael Meissner
2022-03-28 23:59   ` Segher Boessenkool
2022-03-29 17:26     ` Michael Meissner

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