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From: Michael Meissner <meissner@linux.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Michael Meissner <meissner@linux.ibm.com>,
	gcc-patches@gcc.gnu.org, David Edelsohn <dje.gcc@gmail.com>,
	Peter Bergner <bergner@linux.ibm.com>,
	Will Schmidt <will_schmidt@vnet.ibm.com>
Subject: Re: [PATCH 1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
Date: Mon, 28 Mar 2022 18:30:41 -0400	[thread overview]
Message-ID: <YkI3ER1B50EUibug@toto.the-meissners.org> (raw)
In-Reply-To: <20220328171409.GM614@gate.crashing.org>

On Mon, Mar 28, 2022 at 12:14:09PM -0500, Segher Boessenkool wrote:
> On Mon, Mar 28, 2022 at 12:26:02PM -0400, Michael Meissner wrote:
> > However on power9 and power10 it generates:
> > 
> > 	;; vec_splats (vec_extract (src, 0))
> > 	mfvsld 3,34
> > 	mtvsrdd 34,9,9
> > 
> > 	;; vec_splats (vec_extract (src, 1))
> > 	mfvsrd 9,34
> > 	mtvsrdd 34,9,9
> > 
> > This is due to the power9 having the mfvsrld instruction which can extract
> > either 64-bit element into a GPR.  While there are alternatives for both
> > vector registers and GPR registers, the register allocator prefers to put
> > DImode into GPR registers.
> 
> As I said in comment 2 in the PR, it is because we do not have this
> pattern yet, we only have vec_concat.  The instruction combiner tries
> to use this pattern, but it doesn't exist :-)

Ok.  I will create that function and see if it works.

> > +;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
> > +;; PR target/99293
> > +(define_insn "*vsx_splat_const_extract_<mode>"
> > +  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
> > +	(vec_duplicate:VSX_D
> > +	 (vec_select:<VS_scalar>
> > +	  (match_operand:VSX_D 1 "vsx_register_operand" "wa")
> > +	  (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
> > +  "VECTOR_MEM_VSX_P (<MODE>mode)"
> > +{
> > +  int which_word = INTVAL (operands[2]);
> 
> dword, not word.

Ok.

> > +  if (!BYTES_BIG_ENDIAN)
> > +    which_word = 1 - which_word;
> > +
> > +  operands[3] = GEN_INT (which_word ? 3 : 0);
> > +  return "xxpermdi %x0,%x1,%x1,%3";
> 
> Please use gen_vsx_xxspltd_v2di, instead.  Which itself should not use
> an unspec of course, but that is another patch.

There is also vsx_concat_<mode>_3 which does not use an UNSPEC.  Maybe
eventually rewrite vsx_xxspltd_v2di to be a define_insn_and_split.

> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/pr99293.c
> > @@ -0,0 +1,36 @@
> > +/* { dg-do compile { target powerpc*-*-* } } */
> 
> Don't.  This is gcc.target/powerpc/ already.

Ok.

> > +/* { dg-final { scan-assembler-times "xxpermdi" 4 } } */
> 
> \m \M

Ok.

-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com

  reply	other threads:[~2022-03-28 22:41 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-28 16:24 [PATCH 0/4] Optimize vec_splats of vec_extract, PR target/99293 Michael Meissner
2022-03-28 16:26 ` [PATCH 1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293 Michael Meissner
2022-03-28 17:14   ` Segher Boessenkool
2022-03-28 22:30     ` Michael Meissner [this message]
2022-03-28 23:25       ` Segher Boessenkool
2022-03-28 16:27 ` [PATCH 2/4] Make vsx_splat_<mode>_reg use correct insn attributes, PR target/99293 Michael Meissner
2022-03-28 20:28   ` Segher Boessenkool
2022-03-30 22:41     ` Michael Meissner
2022-04-01 17:21       ` Segher Boessenkool
2022-03-28 16:28 ` [PATCH 3/4] Make vsx_extract_<mode> use correct insn attributes, PR target 99293 Michael Meissner
2022-03-28 22:06   ` Segher Boessenkool
2022-03-30 22:58     ` Michael Meissner
2022-03-28 16:28 ` [PATCH 4/4] Allow vsx_extract_<mode> to use Altivec registers, PR target/99293 Michael Meissner
2022-03-28 23:59   ` Segher Boessenkool
2022-03-29 17:26     ` Michael Meissner

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