From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id 4F5EB3858405 for ; Wed, 30 Mar 2022 11:30:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4F5EB3858405 Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-491-fOwMZQt4ObabkBHHPE78XA-1; Wed, 30 Mar 2022 07:30:37 -0400 X-MC-Unique: fOwMZQt4ObabkBHHPE78XA-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 4BF7B3803503; Wed, 30 Mar 2022 11:30:37 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.15]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0953F400E10D; Wed, 30 Mar 2022 11:30:36 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 22UBUYLi158898 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 30 Mar 2022 13:30:34 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 22UBUXqh158897; Wed, 30 Mar 2022 13:30:33 +0200 Date: Wed, 30 Mar 2022 13:30:33 +0200 From: Jakub Jelinek To: Richard Biener Cc: GCC Patches Subject: Re: [wwwdocs] Document zero width bit-field passing ABI changes in gcc-12/changes.html [PR104796] Message-ID: Reply-To: Jakub Jelinek References: MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.11.54.2 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Mar 2022 11:30:49 -0000 On Wed, Mar 30, 2022 at 01:00:43PM +0200, Richard Biener wrote: > > --- a/htdocs/gcc-12/changes.html > > +++ b/htdocs/gcc-12/changes.html > > @@ -28,6 +28,31 @@ a work-in-progress.

> > > >

Caveats

> >
    > > +
  • > > + An ABI incompatibility between C and > > + C++ when passing or returning by value certain aggregates with zero > > + width bit-fields has been discovered on various targets. > > "containing zero width bit-fields"? > > > + As mentioned in PR102024, > > + since the PR42217 fix in > > + GCC 4.5 the C++ front-end has been removing zero width bit-fields > > + from the internal representation of the aggregates after the layout of those > > + aggregates, but the C front-end kept them, so passing e.g. > > + struct S { float a; int : 0; float b; } or > > + struct T { float c; int : 0; } by value could differ > > + between C and C++. Starting with GCC 12 the C++ front-end no longer > > + removes those bit-fields from the internal representation and > > + per clarified psABI some targets have been changed, so that they > > + either ignore those bit-fields in the argument passing by value > > + decisions in both C and C++, or they always take them into account. > > + x86-64, ARM and AArch64 will always ignore them (so there is > > + a C ABI incompatibility between GCC 11 and earlier with GCC 12 or > > + later), PowerPC64 ELFv2 and S/390 always take them into account > > + (so there is a C++ ABI incompatibility, GCC 4.4 and earlier compatible > > + with GCC 12 or later, incompatible with GCC 4.5 through GCC 11). > > + RISC-V has changed the handling of these already starting with GCC 10. > > + GCC 12 on the above targets will report such incompatibilities as > > + warnings or other diagnostics unless -Wno-psabi is used. > > +
    • > > Otherwise LGTM. Thanks, changed and committed. > The case with float a; int :0; float b; looks quite artificial - are there cases > where { int a0 : 24; int a1 : 8; int :0; int b0 : 24; int b1 : 8; } > are affected? Thus > cases where people might actually use :0 which is inbetween bitfields? At > least I can't convince GCC on x86_64 to pass those differently, on x86_64, we've actually been ignoring zero width bitfields on the 64-bit word boundaries since forever due to the way how it was implemented: /* Bitfields are always classified as integer. Handle them early, since later code would consider them to be misaligned integers. */ if (DECL_BIT_FIELD (field)) { for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8; i < ((int_bit_position (field) + (bit_offset % 64)) + tree_to_shwi (DECL_SIZE (field)) + 63) / 8 / 8; i++) classes[i] = merge_classes (X86_64_INTEGER_CLASS, classes[i]); } where the loop would do nothing when the bit_offset + int_bit_position is 64-bit aligned and DECL_SIZE (field) is integer_zerop. So it was just the zero width bitfields at other offsets, and those were treated as merging the containing 64-bit word with INTEGER class. So, if there were just integer bitfields in that 64-bit word, merging it with INTEGER class wouldn't change anything. E.g. powerpc64le or s390x care about "homogenous" structures, whether everything is float (or double?) and those bit-fields make it not homogenous, so again one needs mixing float or double with : 0 bitfields (which must be integral in C/C++). So yes, it is hopefully rare if not non-existent in real-world code, but apparently it has been already discovered before (in 2015 LLVM has been changed on s390 to match the GCC C/C++ ABI incompatibility, and in GCC 10 riscv has been changed, unfortunately in neither case a discussion has been held on whether that is intentional or not). As for the remaining arches, I believe mips n32/n64 are effected and fuzzy (they have a rule that if a 64-bit word in a struct is double and isn't part of union, then it is passed in floating point regs, otherwise in integer, and similarly to the non-clarified x86-64 psABI, it is unclear if int :0 count in that and if they do, whether they are part of the following or preceeding 64-bit word (as they live in a boundary between them); then they have a rule that structures containing one or two float members is returned one way, otherwise different, in that case I'd say it is more like the ppc64le/s390x homogenous aggregate case), loongarch probably should decide what they want, ia64 and iq2000 are maybe effect but I really don't care about those, and rest is hopefully unaffected. Jakub