From: Michael Meissner <meissner@linux.ibm.com>
To: Peter Bergner <bergner@linux.ibm.com>
Cc: Segher Boessenkool <segher@kernel.crashing.org>,
Michael Meissner <meissner@linux.ibm.com>,
gcc-patches@gcc.gnu.org, "Kewen.Lin" <linkw@linux.ibm.com>,
David Edelsohn <dje.gcc@gmail.com>,
Will Schmidt <will_schmidt@vnet.ibm.com>
Subject: Re: [PATCH 1/3] Disable generating store vector pair.
Date: Tue, 7 Jun 2022 23:16:43 -0400 [thread overview]
Message-ID: <YqAUmwAO1MCAnQMb@toto.the-meissners.org> (raw)
In-Reply-To: <85479b53-7c81-1bda-e63d-33497accc58e@linux.ibm.com>
On Tue, Jun 07, 2022 at 07:59:34PM -0500, Peter Bergner wrote:
> On 6/7/22 4:24 PM, Segher Boessenkool wrote:
> > On Tue, Jun 07, 2022 at 04:17:04PM -0500, Peter Bergner wrote:
> >> I think I mentioned this offline, but I'd prefer a negative target flag,
> >> something like TARGET_NO_STORE_VECTOR_PAIR that defaults to off, meaning we'd
> >> generate stxvp by default.
> >
> > NAK. All negatives should be -mno-xxx with -mxxx the corresponding
> > positive. All of them.
>
> That's not what I was asking for. I totally agree that -mno-store-vector-pair
> should disable generating stxvp and that -mstore-vector-pair should enable
> generating it. What I asked for was that the internal flag we use to enable
> and disable it should be a negative flag, where TARGET_NO_STORE_VECTOR_PAIR is
> true when we use -mno-store-vector-pair and false when using -mstore-vector-pair.
> That way we can add that flag to power10's rs6000-cpu.def entry and then we're
> done. What I don't want to have to do is that if/when power87 is released, we
> still have to add TARGET_STORE_VECTOR_PAIR its rs6000-cpu.def entry just to
> get stxvp insns generated. That adds a cost to every cpu after power10 since
> we'd have to remember to add that flag to every follow-on cpu.
FWIW, I really dislike having negative flags like that (just talking about the
option mask internals, not the user option).
I don't view the cost to add one postive flag to the next CPU as bad, as it
will be a one time cost. Presumably it would be set also next++ CPU. This is
like power8 is all of the power7 flags + new flags. Power9 is all of the
power8 flags + new flags. I.e. in general it is cumulative. Yes, I'm aware
there are times when there are breaks, but hopefully those are rare.
Otherwise it is like the mess with -mpower8-fusion, where going from power8 to
power9 we have to clear the fusion flag. If store vector pair is a postive
flag, then it isn't set in power10 flags, but it might be set in next cpu
flags. But if it is a negative flag, we have to explicitly clear it.
We can do it, but I just prefer to go with the positive flag approach.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com
next prev parent reply other threads:[~2022-06-08 3:16 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 0:53 [PATCH, 0/3] " Michael Meissner
2022-06-07 0:55 ` [PATCH 1/3] " Michael Meissner
2022-06-07 20:28 ` will schmidt
2022-06-07 21:17 ` Peter Bergner
2022-06-07 21:24 ` Segher Boessenkool
2022-06-08 0:59 ` Peter Bergner
2022-06-08 3:16 ` Michael Meissner [this message]
2022-06-08 14:49 ` will schmidt
2022-06-08 14:58 ` Peter Bergner
2022-06-07 23:20 ` Michael Meissner
2022-06-07 0:55 ` [PATCH 2/3] Disable generating load/store vector pairs for block copies Michael Meissner
2022-06-07 20:28 ` will schmidt
2022-06-07 0:56 ` [PATCH 3/3] Adjust MMA tests to account for no store vector pair Michael Meissner
2022-06-07 20:28 ` will schmidt
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