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From: Michael Meissner <meissner@linux.ibm.com>
To: gcc-patches@gcc.gnu.org,
	Michael Meissner <meissner@linux.ibm.com>,
	Segher Boessenkool <segher@kernel.crashing.org>,
	"Kewen.Lin" <linkw@linux.ibm.com>,
	David Edelsohn <dje.gcc@gmail.com>,
	Peter Bergner <bergner@linux.ibm.com>,
	Will Schmidt <will_schmidt@vnet.ibm.com>
Subject: [PATCH] Remove setting -mblock-ops-vector-pair on power10.
Date: Thu, 21 Jul 2022 02:42:29 -0400	[thread overview]
Message-ID: <Ytj1VQ5aTY+Ap4BW@toto.the-meissners.org> (raw)

Remove setting -mblock-ops-vector-pair on power10.

Testing has shown that using the load vector pair and store vector pair
instructions for block moves has some performance issues on power10.  This
patch does not set this option by default.  If it is a win in other
machines in the future, this flag can be set in the ISA options.

This patch modifies a previous patch that attempted to do the same thing
but the previous patch was flawed in that it would generate the load
vector pair and store vector pair instructions if we are tuning for a
different machine.

I have tested this patch on power10 systems (with long double set to IEEE
128-bit and also with long double set to IBM 128-bit).  Can I check this patch
into the trunk and back port to older GCC releases?

2022-07-21   Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/rs6000.cc (rs6000_option_override_internal):
	Do not enable -mblock-ops-vector-pair by default on power10.
---
 gcc/config/rs6000/rs6000.cc | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3ff16b8ae04..667f83b1dfd 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4139,17 +4139,6 @@ rs6000_option_override_internal (bool global_init_p)
 	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX;
     }
 
-  if (!(rs6000_isa_flags_explicit & OPTION_MASK_BLOCK_OPS_VECTOR_PAIR))
-    {
-      /* Do not generate lxvp and stxvp on power10 since there are some
-	 performance issues.  */
-      if (TARGET_MMA && TARGET_EFFICIENT_UNALIGNED_VSX
-	  && rs6000_tune != PROCESSOR_POWER10)
-	rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
-      else
-	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
-    }
-
   /* Use long double size to select the appropriate long double.  We use
      TYPE_PRECISION to differentiate the 3 different long double types.  We map
      128 into the precision used for TFmode.  */
-- 
2.35.3


-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com

             reply	other threads:[~2022-07-21  6:42 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-21  6:42 Michael Meissner [this message]
2022-07-21 20:50 ` Segher Boessenkool

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