From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id D4CBB3858D32 for ; Thu, 6 Apr 2023 11:37:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D4CBB3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1680781044; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=SyFHlJau9dGs/S05D+D2dSetJSF5rGzFlZkEMqcNzKM=; b=SLgAD1fxhXqJUz67GcsNIty3hoxwU8Z94zb0u/GioasGJ0bBQKUhmCIy43/0WIgY1g0iHo 15ivLPltHSOqj4fGaTpenRU1I77EctbthqLftjJzabxs27Ezep71XMax1H2WmYHhPpPXWv EjZF6pS28ox99ayDkWfgl8pl4Iqf81A= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-394-2z2sVRCYNG25hA_xb58SWg-1; Thu, 06 Apr 2023 07:37:19 -0400 X-MC-Unique: 2z2sVRCYNG25hA_xb58SWg-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 13D6A1C0754C; Thu, 6 Apr 2023 11:37:19 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.16]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AD7071121314; Thu, 6 Apr 2023 11:37:18 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 336BbFsZ3998283 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Thu, 6 Apr 2023 13:37:15 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 336BbEpI3998282; Thu, 6 Apr 2023 13:37:14 +0200 Date: Thu, 6 Apr 2023 13:37:13 +0200 From: Jakub Jelinek To: Eric Botcazou Cc: Jeff Law , Richard Biener , Richard Sandiford , gcc-patches@gcc.gnu.org Subject: Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040] Message-ID: Reply-To: Jakub Jelinek References: <2876279.e9J7NaK4W3@fomalhaut> <2220543.iZASKD2KPV@fomalhaut> MIME-Version: 1.0 In-Reply-To: <2220543.iZASKD2KPV@fomalhaut> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Apr 06, 2023 at 12:51:20PM +0200, Eric Botcazou wrote: > > If we want to fix it in the combiner, I think the fix would be following. > > The optimization is about > > (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) > > and IMHO we can only optimize it into > > (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) > > if we know that the upper bits of the REG are zeros. > > The reasoning is that, for WORD_REGISTER_OPERATIONS, the subword AND operation > is done on the full word register, in other words that it's in effect: > > (subreg:SI (and:SI (reg:SI xxx) (const_int 0x84c)) 0) > > that is equivalent to the initial RTL so correct for WORD_REGISTER_OPERATIONS. If the (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) to (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) transformation is kosher for WORD_REGISTER_OPERATIONS, then I guess the invalid operation is then in simplify_context::simplify_binary_operation_1 case AND: ... if (HWI_COMPUTABLE_MODE_P (mode)) { HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, mode); HOST_WIDE_INT nzop1; if (CONST_INT_P (trueop1)) { HOST_WIDE_INT val1 = INTVAL (trueop1); /* If we are turning off bits already known off in OP0, we need not do an AND. */ if ((nzop0 & ~val1) == 0) return op0; } We have there op0==trueop0 (reg:HI 175) and op1==trueop1 (const_int 2124 [0x84c]). We then for integral? modes smaller than word_mode would then need to actually check nonzero_bits in the word_mode (on paradoxical subreg of trueop0?). If INTVAL (trueop1) is >= 0, then I think just doing nonzero_bits in the wider mode would be all we need (although the subsequent (nzop1 & nzop0) == 0 case probably wants to have the current nonzero_bits calls), not really sure what for WORD_REGISTER_OPERATIONS means AND with a constant which has the most significant bit set for the upper bits. So, perhaps just in the return op0; case add further code for WORD_REGISTER_OPERATIONS and sub-word modes which will call nonzero_bits again for the word mode and decide if it is still safe. > > Now, this patch fixes the PR, but certainly generates worse (but correct) > > code than the dse.cc patch. So perhaps we want both of them? > > What happens if you disable the step I mentioned (patchlet attached)? That patch doesn't change anything at all on the testcase, it is still miscompiled. Jakub