From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id A92953858D28 for ; Thu, 6 Apr 2023 15:12:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A92953858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 336EwRQq010179; Thu, 6 Apr 2023 15:12:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=date : from : to : subject : message-id : mime-version : content-type; s=pp1; bh=qRU4ulEmj5Bp06CAIJTMsn5Wh1ySs8DQhDVx2D45hJY=; b=T+sDlQGaGtNealmXwvnW5j+hNQiArZezANKInFNab55cityHMjRhiMYdyRI5+n+lpnky UPhjtu4Xjxk0gedIqHWobBgRsLIMssaZcUOOtSV0pa6Uh0RKfSPOAkr83JZq3QkJVk6N azJIRTJrj1fmTHfokWEyEVstR14SwT5NvNYOl3PkCckN35VFFZlrBNE5CTVHr4vw+97L VKzI8esbfL7Nb1PeFNp5YOHC0v7+TuOMKZSOF7yAmtJUKiNrank6IZRbjiRjmkHGmjhc 9tHC+FJm/jtJRFoOWRxToYFjIgA7uzVl+LD2398i/QPgR3sf9+Y4lBbh8Z6GG7ugpRI9 VQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3psyst9evu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Apr 2023 15:12:18 +0000 Received: from m0098396.ppops.net (m0098396.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 336EwtLi013472; Thu, 6 Apr 2023 15:12:18 GMT Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com [169.55.85.253]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3psyst9ev8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Apr 2023 15:12:17 +0000 Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1]) by ppma01wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 336F4OOp024935; Thu, 6 Apr 2023 15:12:16 GMT Received: from smtprelay03.wdc07v.mail.ibm.com ([9.208.129.113]) by ppma01wdc.us.ibm.com (PPS) with ESMTPS id 3ppc8838k1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Apr 2023 15:12:16 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 336FCDRw31195784 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Apr 2023 15:12:14 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B6E2658065; Thu, 6 Apr 2023 15:12:13 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 207555805C; Thu, 6 Apr 2023 15:12:13 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.160.59.115]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Thu, 6 Apr 2023 15:12:13 +0000 (GMT) Date: Thu, 6 Apr 2023 11:12:11 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt , chip.kerchner@ibm.com Subject: PR target/70243: Do not generate fmaddfp and fnmsubfp Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt , chip.kerchner@ibm.com MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 3GX1BaHgp3H1jT16betoYJ4XIzJdgoYN X-Proofpoint-GUID: S-QQPEj9CxvkdH4jq6xtWAAswbwvMZFC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-06_08,2023-04-06_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 adultscore=0 impostorscore=0 clxscore=1011 mlxlogscore=999 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304060134 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_MANYTO,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The Altivec instructions fmaddfp and fnmsubfp have different rounding behaviors than the VSX xvmaddsp and xvnmsubsp instructions. In particular, generating these instructions seems to break Eigen. GCC has generated the Altivec fmaddfp and fnmsubfp instructions on VSX systems as an alternative to the xsmadd{a,m}sp and xsnmsub{a,m}sp instructions. The advantage of the Altivec instructions is that they are 4 operand instructions (i.e. the target register does not have to overlap with one of the input registers). The advantage is it can eliminate an extra move instruction. The disadvantage is it does round the same was as the VSX instructions. This patch eliminates the generation of the Altivec fmaddfp and fnmsubfp instructions as alternatives in the VSX instruction insn support, and in the Altivec insns it adds a test to prevent the insn from being used if VSX is available. I also added a test to the regression test suite. I have done bootstrap builds on power9 little endian (with both IEEE long double and IBM long double). I have also done the builds and test on a power8 big endian system (testing both 32-bit and 64-bit code generation). Chip has verified that it fixes the problem that Eigen encountered. Can I check this into the master GCC branch? After a burn-in period, can I check this patch into the active GCC branches? Thanks in advance. 2023-04-06 Michael Meissner gcc/ PR target/70243 * config/rs6000/altivec.md (altivec_fmav4sf4): Add a test to prevent fmaddfp and fnmsubfp from being generated on VSX systems. (altivec_vnmsubfp): Likewise. * config/rs6000/rs6000.md (vsx_fmav4sf4): Do not generate fmaddfp or fnmsubfp. (vsx_nfmsv4sf4): Likewise. gcc/testsuite/ PR target/70243 * gcc.target/powerpc/pr70243.c: New test. --- gcc/config/rs6000/altivec.md | 9 +++-- gcc/config/rs6000/vsx.md | 29 +++++++-------- gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ++++++++++++++++++++++ 3 files changed, 61 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr70243.c diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 49b0c964f4d..63eab228d0d 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -750,12 +750,15 @@ (define_insn "altivec_vsel4" ;; Fused multiply add. +;; If we are using VSX instructions, do not generate the vmaddfp instruction +;; since is has different rounding behavior than the xvmaddsp instruction. + (define_insn "*altivec_fmav4sf4" [(set (match_operand:V4SF 0 "register_operand" "=v") (fma:V4SF (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v") (match_operand:V4SF 3 "register_operand" "v")))] - "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" + "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX" "vmaddfp %0,%1,%2,%3" [(set_attr "type" "vecfloat")]) @@ -984,6 +987,8 @@ (define_insn "vstril_p_direct_" [(set_attr "type" "vecsimple")]) ;; Fused multiply subtract +;; If we are using VSX instructions, do not generate the vnmsubfp instruction +;; since is has different rounding behavior than the xvnmsubsp instruction. (define_insn "*altivec_vnmsubfp" [(set (match_operand:V4SF 0 "register_operand" "=v") (neg:V4SF @@ -991,7 +996,7 @@ (define_insn "*altivec_vnmsubfp" (match_operand:V4SF 2 "register_operand" "v") (neg:V4SF (match_operand:V4SF 3 "register_operand" "v")))))] - "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" + "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX" "vnmsubfp %0,%1,%2,%3" [(set_attr "type" "vecfloat")]) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0865608f94a..03c1d787b6c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2009,22 +2009,20 @@ (define_insn "*vsx_tsqrt2_internal" "xtsqrtp %0,%x1" [(set_attr "type" "")]) -;; Fused vector multiply/add instructions. Support the classical Altivec -;; versions of fma, which allows the target to be a separate register from the -;; 3 inputs. Under VSX, the target must be either the addend or the first -;; multiply. +;; Fused vector multiply/add instructions. Do not use the classical Altivec +;; versions of fma. Those instructions allows the target to be a separate +;; register from the 3 inputs, but they have different rounding behaviors. (define_insn "*vsx_fmav4sf4" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa") (fma:V4SF - (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v") - (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v") - (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))] + (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa") + (match_operand:V4SF 2 "vsx_register_operand" "wa,0") + (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))] "VECTOR_UNIT_VSX_P (V4SFmode)" "@ xvmaddasp %x0,%x1,%x2 - xvmaddmsp %x0,%x1,%x3 - vmaddfp %0,%1,%2,%3" + xvmaddmsp %x0,%x1,%x3" [(set_attr "type" "vecfloat")]) (define_insn "*vsx_fmav2df4" @@ -2066,18 +2064,17 @@ (define_insn "*vsx_nfma4" [(set_attr "type" "")]) (define_insn "*vsx_nfmsv4sf4" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa") (neg:V4SF (fma:V4SF - (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v") - (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v") + (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa") + (match_operand:V4SF 2 "vsx_register_operand" "wa,0") (neg:V4SF - (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))] + (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))] "VECTOR_UNIT_VSX_P (V4SFmode)" "@ xvnmsubasp %x0,%x1,%x2 - xvnmsubmsp %x0,%x1,%x3 - vnmsubfp %0,%1,%2,%3" + xvnmsubmsp %x0,%x1,%x3" [(set_attr "type" "vecfloat")]) (define_insn "*vsx_nfmsv2df4" diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c new file mode 100644 index 00000000000..1dfc13a8864 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70243.c @@ -0,0 +1,41 @@ +/* { dg-do compile */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx" } */ + +/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp. These + instructions have different rounding modes than the VSX instructions + xvmaddsp and xvnmsubsp. These tests are written where the 3 inputs and + target are all separate registers. Because fmaddfp and fnmsubfp are no + longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp + instruction followed by a move operation. */ + +#include + +vector float +do_add1 (vector float dummy, vector float a, vector float b, vector float c) +{ + return (a * b) + c; +} + +vector float +do_nsub1 (vector float dummy, vector float a, vector float b, vector float c) +{ + return -((a * b) - c); +} + +vector float +do_add2 (vector float dummy, vector float a, vector float b, vector float c) +{ + return vec_madd (a, b, c); +} + +vector float +do_nsub2 (vector float dummy, vector float a, vector float b, vector float c) +{ + return vec_nmsub (a, b, c); +} + +/* { dg-final { scan-assembler "xvmaddsp" } } */ +/* { dg-final { scan-assembler "xvnmsubsp" } } */ +/* { dg-final { scan-assembler-not "fmaddfp" } } */ +/* { dg-final { scan-assembler-not "fnmsubfp" } } */ -- 2.39.2 -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meissner@linux.ibm.com