From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id 986A03858C20 for ; Tue, 11 Apr 2023 10:12:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 986A03858C20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1681207921; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=RlrlfzlLoIB/eljB+E9E9myEdghRbJ0QFJn754M9G4k=; b=OYgJqI4e2q8AXzuqF0SrddFyYm6Q74Wio2BVOcXUaPtCj4qAljrsg7Py0zXabqIws0RoWb oxyOSZMU62hzmEF4E0REhsfp70XbhK2HxLxArjHOyLbisbM7v77XkMZAyKpEepZcemcocO hU11SGKwLaeu0cFmf5rjd9zsx4+Py30= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-595-eP8WC-RvMR24uDaq6ql_SA-1; Tue, 11 Apr 2023 06:11:54 -0400 X-MC-Unique: eP8WC-RvMR24uDaq6ql_SA-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id AC1A2185A791; Tue, 11 Apr 2023 10:11:53 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.16]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 65628407D445; Tue, 11 Apr 2023 10:11:53 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 33BABmCH2466379 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Tue, 11 Apr 2023 12:11:49 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 33BABlgv2466378; Tue, 11 Apr 2023 12:11:47 +0200 Date: Tue, 11 Apr 2023 12:11:46 +0200 From: Jakub Jelinek To: "juzhe.zhong@rivai.ai" Cc: jeffreyalaw , gcc-patches , "kito.cheng" , palmer , "richard.sandiford" , rguenther , Vladimir Makarov Subject: Re: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit Message-ID: Reply-To: Jakub Jelinek References: <20230410144808.324346-1-juzhe.zhong@rivai.ai> <89f088ec-8692-01f5-0395-5a66ddf085d7@gmail.com> <47D962C7C724E3A2+20230410231445834316202@rivai.ai> <33437CE6C30D8818+20230411174615272541216@rivai.ai> MIME-Version: 1.0 In-Reply-To: <33437CE6C30D8818+20230411174615272541216@rivai.ai> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Apr 11, 2023 at 05:46:15PM +0800, juzhe.zhong@rivai.ai wrote: > I am not sure whether aggregate type without a tuple mode can work for us. > Here is the example: > > We already had a vector type "vint8mf8_t", the corresponding mode is VNx1SImode. > > Now we have an intrinsic as following: > vint8mf8x2_t test_vlseg2e8_v_i8mf8(const int8_t *base, size_t vl) { > return __riscv_vlseg2e8_v_i8mf8(base, vl); > } > > This intrinsic is suppose generate a "vlseg2e8.v" instructions and dest operand of the intrinsic should be 2 continguous registers. > > Another intrinsic: > vint8mf8x3_t test_vlseg3e8_v_i8mf8(const int8_t *base, size_t vl) { > return __riscv_vlseg3e8_v_i8mf8(base, vl); > } > > This intrinsic is suppose generate a "vlseg3e8.v" instructions and dest operand of the intrinsic should be 3 continguous registers. > > Now, my plan is to build_array_type for both "vint8mf8x2_t" and "vint8mf8x3_t" and make their TYPE_MODE is "VNx2x1SI" and "VNx3x1SI" corresponding like ARM SVE. > Then define the RTL pattern which has dest operand is a register_operand with mode "VNx2x1SI" and "VNx3x1SI". Then we can do the codegen. Another possibility would be just make it explicit in the RTL that it sets 3 VNx1SI mode REGs rather than one, as long as there is some way to tell RA that they need to be consecutive. CCing Vlad on that. Jakub