From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id ADD003858D28 for ; Wed, 12 Apr 2023 06:21:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ADD003858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1681280495; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=FAJ8Csv0tULRQ2SYUi554xUqba6IKAfiCCnzCRIYxzw=; b=BUXiA8nVPn0udraTQAEnzh1X7K2ZL/U01LNv/sqROAH9AI9jgZTIKH05rq5MC8MF8Jbq2g qdUoE4QjimRhuK1Y3OjBNzA9JoFW9gwsjwn9defByJRoFZOw454qMYqmwprxPeugSIw/fA vkafjTMzUP05/VlT9G0QUmxyBvp9upA= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-561-XrVi9W7aMEiB17RTcZQDgA-1; Wed, 12 Apr 2023 02:21:32 -0400 X-MC-Unique: XrVi9W7aMEiB17RTcZQDgA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id AB9C53847080; Wed, 12 Apr 2023 06:21:31 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.16]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6508F2027043; Wed, 12 Apr 2023 06:21:31 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 33C6LShL1517079 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 12 Apr 2023 08:21:28 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 33C6LQPn1517078; Wed, 12 Apr 2023 08:21:26 +0200 Date: Wed, 12 Apr 2023 08:21:26 +0200 From: Jakub Jelinek To: Jeff Law Cc: Eric Botcazou , gcc-patches@gcc.gnu.org, Richard Biener , Richard Sandiford Subject: Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040] Message-ID: Reply-To: Jakub Jelinek References: <2220543.iZASKD2KPV@fomalhaut> <3412470.QJadu78ljV@fomalhaut> <8d3c3861-c291-e762-a2a8-0b520f39a7e3@gmail.com> <965831db-ac9e-cc5e-3459-08b6b70fd577@gmail.com> MIME-Version: 1.0 In-Reply-To: <965831db-ac9e-cc5e-3459-08b6b70fd577@gmail.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Apr 11, 2023 at 07:26:07PM -0600, Jeff Law wrote: > I did bootstrap on riscv, but not a regression test, that's spinning right > now. > > Jeff > diff --git a/gcc/combine.cc b/gcc/combine.cc > index 22bf8e1ec89..c41d8a09b3b 100644 > --- a/gcc/combine.cc > +++ b/gcc/combine.cc > @@ -10055,9 +10055,10 @@ simplify_and_const_int_1 (scalar_int_mode mode, rtx varop, > > /* See what bits may be nonzero in VAROP. Unlike the general case of > a call to nonzero_bits, here we don't care about bits outside > - MODE. */ > + MODE unless WORD_REGISTER_OPERATIONS is true. */ I would have expected something like WORD_REGISTER_OPERATIONS && known_le (GET_MODE_PRECISION (mode), BITS_PER_WORD) as the condition to use word_mode, rather than just WORD_REGISTER_OPERATIONS. In both spots. Because larger modes should be used as is, not a narrower word_mode instead of them. > - nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); > + enum machine_mode tmode = WORD_REGISTER_OPERATIONS ? word_mode : mode; > + nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode); > > /* Turn off all bits in the constant that are known to already be zero. > Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > index 3b33afa2461..5f6f70491d8 100644 > --- a/gcc/simplify-rtx.cc > +++ b/gcc/simplify-rtx.cc > @@ -3752,7 +3752,10 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, > return op0; > if (HWI_COMPUTABLE_MODE_P (mode)) > { > - HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, mode); > + /* When WORD_REGISTER_OPERATIONS is true, we need to know the > + nonzero bits in WORD_MODE rather than MODE. */ > + HOST_WIDE_INT nzop0 > + = nonzero_bits (trueop0, WORD_REGISTER_OPERATIONS ? word_mode : mode); > HOST_WIDE_INT nzop1; > if (CONST_INT_P (trueop1)) > { Regarding my earlier comments for this spot, the later code does nzop1 = nonzero_bits (trueop1, mode); /* If we are clearing all the nonzero bits, the result is zero. */ if ((nzop1 & nzop0) == 0 && !side_effects_p (op0) && !side_effects_p (op1)) return CONST0_RTX (mode); and because nonzero_bits in word_mode if it is wider might have just more bits set above mode, but nzop1 will not have those bits set, I think it is fine the way you wrote it (except for the precision check). Jakub