From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id E1D2D385B528 for ; Mon, 21 Aug 2023 08:09:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1D2D385B528 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1692605352; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6k31pSP+6++Blj9P+MMiJA/NNBk1K+5wURgeO4V35oY=; b=WqhRZ7AV7oH9fpuqunzfD5NAvgjIFD0M+WRf+2IyjVMouRPZsIM1DN8gQsoKvPMFrhJNhq xeGRujweZScj0OKWopdlGiup+CBsGTwPtFpftA/BuVndXw4JVcIuhTljJAbyrXaTbN13LM 2hP7qk3qcV0H2ujQfOA2S8zGYHN/CV0= Received: from mimecast-mx02.redhat.com (66.187.233.73 [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-669-_RLDkIN2M3C5X-jeyhGQNA-1; Mon, 21 Aug 2023 04:09:07 -0400 X-MC-Unique: _RLDkIN2M3C5X-jeyhGQNA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id A43AA2A5955C; Mon, 21 Aug 2023 08:09:06 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.45.224.19]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 563A2140E950; Mon, 21 Aug 2023 08:09:06 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 37L8939t026400 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 21 Aug 2023 10:09:03 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 37L892tI026399; Mon, 21 Aug 2023 10:09:02 +0200 Date: Mon, 21 Aug 2023 10:09:02 +0200 From: Jakub Jelinek To: Richard Biener Cc: Hongtao Liu , ZiNgA BuRgA , haochen.jiang@intel.com, gcc-patches@gcc.gnu.org Subject: Re: Intel AVX10.1 Compiler Design and Support Message-ID: Reply-To: Jakub Jelinek References: <20230808071312.1569559-1-haochen.jiang@intel.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches wrote: > > On Sun, Aug 20, 2023 at 6:44 AM ZiNgA BuRgA via Gcc-patches > > wrote: > > > > > > Hi, > > > > > > With the proposed design of these switches, how would I restrict AVX10.1 > > > to particular AVX-512 subsets? > > We can't, avx10.1 is taken as an indivisible ISA which contains all > > AVX512 related instructions. > > > > > We’ve been taking these cases as bugs (but yes, intrinsics are still allowed, so in some cases it might prove difficult to guarantee this). > > intel sde support avx10.1-256 target which can be used to validate the > > binary(if there's invalid 512-bit vector register or 64-bit kmask > > register is used). > > > I don’t see any other way of doing what you want within the constraints of this design. > > It looks like the requirement is that we want a > > -mavx10-vector-width=256(or maybe reuse -mprefer-vector-width=256) > > option that acts on the original -mavx512XXX option to produce > > avx10.1-256 compatible binary. we can't use -mavx10.1-256 since it may > > include avx512fp16 directives and thus not be backward compatible > > SKX/CLX/ICX. > > Yes. Note we cannot really re-purpose -mprefer-vector-width=256 since that > would also make uses of 512bit intrinsics ill-formed. So we'd need a new > flag that would restrict AVX512VL to 256bit, possibly using a common internal > flag for this and the -mavx10.1-256 vector size effect. > > Maybe -mdisable-vector-width-512 or -mavx512vl-for-avx10.1-256 or > -mavx512vl-256? Writing these the last looks most sensible to me? > Note it should combine with -mavx512vl to -mavx512vl-256 to make > -march=native -mavx512vl-256 work (I think we should also allow the > flag together with -mavx10.1*?) > > mavx512vl-256 > Target ... > Disable the 512bit vector ISA subset of AVX512 or AVX10, enable > the 256bit vector ISA subset of AVX512. Wouldn't it be better to have it similarly to other ISA options as something positive, say -mevex512 (the ISA docs talk about EVEX.512, EVEX.256 and EVEX.128)? Have -mavx512f (and anything that implies it right now) imply also -mevex512 but allow -mno-evex512 which wouldn't unset everything dependent on -mavx512f. There is one gotcha, if -mavx512vl isn't enabled in the end, then -mavx512f -mno-evex512 should disable whole TARGET_AVX512F because nothing is left. TARGET_EVEX512 then would guard all TARGET_AVX512* intrinsics which operate on 512-bit vector registers or 64-bit mask registers (in addition to the other TARGET_AVX512* options, perhaps except TARGET_AVX512F), whether the 512-bit modes can be used etc. Jakub