From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 4669E385AC09 for ; Thu, 24 Aug 2023 17:35:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4669E385AC09 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37OHJNhi013495; Thu, 24 Aug 2023 17:35:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=pp1; bh=J/bcwxSiv0Jma+cCkf1FEENH80E0vd0C9w0oavvdMk8=; b=IDZ0Me4txnF/nEuGcCYB9087RRC9FJfz9JUPBCVAoFDpAZkenWXoIGwTq0C6FutCA1jQ WsZUatd4CmBQGe6Doco4AKUf2LUJa01YuUAtwVGTZtNmqrHujooKMKgVkm+6oVchFDVP c+Lhykxn6g7dQIXJrBTN+f0DWYOMMDQE+gSbUIEh54ln6mdUxA94RMv+bkNsTX/IZkxT bFE5cE/L40H5NlY2WeOwoADdE0ARPekoFmKhprqsEsjXOk+hKwNPEq/HN+HODhW1fpQf Z37Up/w0iFKbyxjYu/Z0i3i6nMGwTdqnBpJ+KPr5UQ4lg9VfUjW4PVgEWpwl8/Ka88+V 7A== Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3spbggrhjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Aug 2023 17:35:18 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 37OGdKtC027342; Thu, 24 Aug 2023 17:35:17 GMT Received: from smtprelay06.dal12v.mail.ibm.com ([172.16.1.8]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3sn20ss1gm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Aug 2023 17:35:17 +0000 Received: from smtpav06.wdc07v.mail.ibm.com (smtpav06.wdc07v.mail.ibm.com [10.39.53.233]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 37OHZG4H066082 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 24 Aug 2023 17:35:16 GMT Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 299B158060; Thu, 24 Aug 2023 17:35:16 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8BE6A5804E; Thu, 24 Aug 2023 17:35:15 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.167.115]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Thu, 24 Aug 2023 17:35:15 +0000 (GMT) Date: Thu, 24 Aug 2023 13:35:13 -0400 From: Michael Meissner To: jeevitha Cc: gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, meissner@linux.ibm.com, Peter Bergner Subject: Re: [PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895] Message-ID: Mail-Followup-To: Michael Meissner , jeevitha , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, Peter Bergner References: <460cd2bd-7c82-95d8-c58e-f32da70ab2a9@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <460cd2bd-7c82-95d8-c58e-f32da70ab2a9@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: SSK1Tdg_t_VdWNruCxrGlGX5NEhOAaVt X-Proofpoint-ORIG-GUID: SSK1Tdg_t_VdWNruCxrGlGX5NEhOAaVt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-24_14,2023-08-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxlogscore=674 lowpriorityscore=0 mlxscore=0 clxscore=1011 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308240150 X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Jul 20, 2023 at 10:05:28AM +0530, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > When the user specifies PTImode as an attribute, it breaks. Created > a tree node to handle PTImode types. PTImode attribute helps in generating > even/odd register pairs on 128 bits. > > 2023-07-20 Jeevitha Palanisamy > > gcc/ > PR target/110411 > * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields > to hold PTImode type. > * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node > for PTImode type. > > gcc/testsuite/ > PR target/106895 > * gcc.target/powerpc/pr106895.c: New testcase. It is good as far as it goes, but I suspect we will eventually need to extend it. In particular, the reason people need PTImode is they need the even/odd register layout. What you've done enables users to declare this value. However, it is likely the users (kernel users mostly) will want to use it with the atomic built-in functions that take 16 byte values. So I suspect we will need to add overloads for those built-ins to allow either TImode and PTImode to be used. Note, the PTImode built-in would bypass the TImode parts where they convert a TImode into PTImode. This is the reason PTImode was created in the first place. Due to the calling sequence, TImode could be passed in odd/even (as well as even/odd) register pairs, but the atomic insns and lq/stq need even/odd register pairs. But if you are calling a built-in with PTImode, you don't have to convert it to PTImode. But then the next problem is what happens when people start using it. Do we need to add all of the TImode insns (Add, subtract, and, ior, xor, shifts at the very least)? These are the things I expect people might want to do for memory accessed via atomic insns. Then we get to the thorny problems of load/store on little endian systems, and do we define the order of the two registers. Unfortunately, the lq/stq instructions will load words in the opposite order as plq/pstq. I imagine the kernel folk want to use lq/stq, but we may have to figure out exactly what they want. If we define any form of operation on PTImode, we likely need to define whether register 0 has the high bits or low bits. Sorry to be so negative, but those are a lot of the issues that might come up as people use it. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meissner@linux.ibm.com