From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server28.superhosting.bg (server28.superhosting.bg [217.174.156.11]) by sourceware.org (Postfix) with ESMTPS id CD3FD3858D1E for ; Thu, 7 Sep 2023 20:16:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CD3FD3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dinux.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dinux.eu DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=dinux.eu; s=default; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=fQ8gDpCQkRiWeUyF1oLpg26JZR87bjSrfEFfqz1rP94=; b=auwymrTM93VDaQls0VLHGI6hgq Glxs5zgOoFrtVbDkQUFzhTgBWlLnpTAADgswt7/A9hulzc/iS6e7UGIYPOqHspDwl6DNbE8pQynR4 AVyDkBASzhJgCSxkeMYAgPgnlpzWMajKFmZEgv+014wTBRvgSag0xt4kvbPl3OOUFzvABunF5fVXT 2Y4YhJmGGfu5MKViWzfUlX/EFNxd2/jtJ1jtMz71tCxJDTBUXLySGTrYYIL0yhRJBS5ZJgmQ4t5Zh Jo6Dgda0XHikraPnqqivQ6mTt+NJCWc0oo1ENQ+zw4JK4SM1sJyJbROfZKYeHatdbmxIGkVFnAoF1 VRlfKYBQ==; Received: from 95-42-20-142.ip.btc-net.bg ([95.42.20.142]:56876 helo=localhost) by server28.superhosting.bg with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qeLQa-0004CZ-25; Thu, 07 Sep 2023 23:16:40 +0300 Date: Thu, 7 Sep 2023 23:16:36 +0300 From: Dimitar Dimitrov To: Fei Gao Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jiawei@iscas.ac.cn, Die Li Subject: Re: [PATCH 3/3] [V2] [RISC-V] support cm.mva01s cm.mvsa01 in zcmp Message-ID: References: <20230829083746.1458-1-gaofei@eswincomputing.com> <20230829083746.1458-4-gaofei@eswincomputing.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230829083746.1458-4-gaofei@eswincomputing.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server28.superhosting.bg X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - dinux.eu X-Get-Message-Sender-Via: server28.superhosting.bg: authenticated_id: dimitar@dinux.eu X-Authenticated-Sender: server28.superhosting.bg: dimitar@dinux.eu X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_BODY,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, This patch appears to have caused PR 111259. Regards, Dimitar On Tue, Aug 29, 2023 at 08:37:46AM +0000, Fei Gao wrote: > From: Die Li > > Signed-off-by: Die Li > Co-Authored-By: Fei Gao > > gcc/ChangeLog: > > * config/riscv/peephole.md: New pattern. > * config/riscv/predicates.md (a0a1_reg_operand): New predicate. > (zcmp_mv_sreg_operand): New predicate. > * config/riscv/riscv.md: New predicate. > * config/riscv/zc.md (*mva01s): New pattern. > (*mvsa01): New pattern. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/cm_mv_rv32.c: New test. > --- > gcc/config/riscv/peephole.md | 28 +++++++++++++++++++++ > gcc/config/riscv/predicates.md | 11 ++++++++ > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/zc.md | 22 ++++++++++++++++ > gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c | 23 +++++++++++++++++ > 5 files changed, 85 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c > > diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md > index 0ef0c04410b..92e57f9a447 100644 > --- a/gcc/config/riscv/peephole.md > +++ b/gcc/config/riscv/peephole.md > @@ -38,3 +38,31 @@ > { > operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5])); > }) > + > +;; ZCMP > +(define_peephole2 > + [(set (match_operand:X 0 "a0a1_reg_operand") > + (match_operand:X 1 "zcmp_mv_sreg_operand")) > + (set (match_operand:X 2 "a0a1_reg_operand") > + (match_operand:X 3 "zcmp_mv_sreg_operand"))] > + "TARGET_ZCMP > + && (REGNO (operands[2]) != REGNO (operands[0]))" > + [(parallel [(set (match_dup 0) > + (match_dup 1)) > + (set (match_dup 2) > + (match_dup 3))])] > +) > + > +(define_peephole2 > + [(set (match_operand:X 0 "zcmp_mv_sreg_operand") > + (match_operand:X 1 "a0a1_reg_operand")) > + (set (match_operand:X 2 "zcmp_mv_sreg_operand") > + (match_operand:X 3 "a0a1_reg_operand"))] > + "TARGET_ZCMP > + && (REGNO (operands[0]) != REGNO (operands[2])) > + && (REGNO (operands[1]) != REGNO (operands[3]))" > + [(parallel [(set (match_dup 0) > + (match_dup 1)) > + (set (match_dup 2) > + (match_dup 3))])] > +) > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 3ef09996a85..772f45df65c 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -165,6 +165,17 @@ > (and (match_code "const_int") > (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 13)"))) > > +;; ZCMP predicates > +(define_predicate "a0a1_reg_operand" > + (and (match_operand 0 "register_operand") > + (match_test "IN_RANGE (REGNO (op), A0_REGNUM, A1_REGNUM)"))) > + > +(define_predicate "zcmp_mv_sreg_operand" > + (and (match_operand 0 "register_operand") > + (match_test "TARGET_RVE ? IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) > + : IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) > + || IN_RANGE (REGNO (op), S2_REGNUM, S7_REGNUM)"))) > + > ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate. > (define_predicate "branch_on_bit_operand" > (and (match_code "const_int") > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 8e09df6ff63..aa2b5b960dc 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -132,6 +132,7 @@ > (S0_REGNUM 8) > (S1_REGNUM 9) > (A0_REGNUM 10) > + (A1_REGNUM 11) > (S2_REGNUM 18) > (S3_REGNUM 19) > (S4_REGNUM 20) > diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md > index 8d7de97daad..77b28adde95 100644 > --- a/gcc/config/riscv/zc.md > +++ b/gcc/config/riscv/zc.md > @@ -1433,3 +1433,25 @@ > "TARGET_ZCMP" > "cm.push {ra, s0-s11}, %0" > ) > + > +;; ZCMP mv > +(define_insn "*mva01s" > + [(set (match_operand:X 0 "a0a1_reg_operand" "=r") > + (match_operand:X 1 "zcmp_mv_sreg_operand" "r")) > + (set (match_operand:X 2 "a0a1_reg_operand" "=r") > + (match_operand:X 3 "zcmp_mv_sreg_operand" "r"))] > + "TARGET_ZCMP > + && (REGNO (operands[2]) != REGNO (operands[0]))" > + { return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; } > + [(set_attr "mode" "")]) > + > +(define_insn "*mvsa01" > + [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r") > + (match_operand:X 1 "a0a1_reg_operand" "r")) > + (set (match_operand:X 2 "zcmp_mv_sreg_operand" "=r") > + (match_operand:X 3 "a0a1_reg_operand" "r"))] > + "TARGET_ZCMP > + && (REGNO (operands[0]) != REGNO (operands[2])) > + && (REGNO (operands[1]) != REGNO (operands[3]))" > + { return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; } > + [(set_attr "mode" "")]) > diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c > new file mode 100644 > index 00000000000..2c1b3f9cabf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c > @@ -0,0 +1,23 @@ > +/* { dg-do compile } */ > +/* { dg-options " -Os -march=rv32i_zca_zcmp -mabi=ilp32 " } */ > +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +int > +func (int a, int b); > + > +/* > +**sum: > +** ... > +** cm.mvsa01 s1,s2 > +** call func > +** mv s0,a0 > +** cm.mva01s s1,s2 > +** call func > +** ... > +*/ > +int > +sum (int a, int b) > +{ > + return func (a, b) + func (a, b); > +} > -- > 2.17.1 >