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Mon, 20 Nov 2023 04:26:58 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B3B7C5805A; Mon, 20 Nov 2023 04:26:58 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3770558051; Mon, 20 Nov 2023 04:26:58 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.1.46]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Mon, 20 Nov 2023 04:26:58 +0000 (GMT) Date: Sun, 19 Nov 2023 23:26:56 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: [PATCH 4/4] Add vector pair tests to PowerPC Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Xg7JkpKj1b_71WH-75jIDmCx70NihuJ4 X-Proofpoint-GUID: GKzjRZKTNzNSO-vCCbGfR_ykWGuxzmMv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_01,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=0 mlxscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200029 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The first patch in the vector pair series was previous posted. This patch needs that first patch. The first patch implemented the basic modes, and it allows for initialization of the modes. In addition, I added some optimizations for extracting and setting fields within the vector pair. The second patch in the vector pair series implemented floating point support. The third patch in the vector pair series implemented integer point support. This fourth patch provide new tests to the test suite. When I test a saxpy type loop (a[i] += (b[i] * c[i])), I generally see a 10% improvement over either auto-factorization, or just using the vector types. I have tested these patches on a little endian power10 system. With -vector-size-32 disabled by default, there are no regressions in the test suite. I have also built and run the tests on both little endian power 9 and big endian 9 power systems, and there are no regressions. Can I check these patches into the master branch? 2023-11-19 Michael Meisner gcc/ * gcc.target/powerpc/vector-size-32-1.c: New test. * gcc.target/powerpc/vector-size-32-2.c: New test. * gcc.target/powerpc/vector-size-32-3.c: New test. * gcc.target/powerpc/vector-size-32-4.c: New test. * gcc.target/powerpc/vector-size-32-5.c: New test. * gcc.target/powerpc/vector-size-32-6.c: New test. * gcc.target/powerpc/vector-size-32-7.c: New test. --- .../gcc.target/powerpc/vector-size-32-1.c | 106 ++++++++++++++ .../gcc.target/powerpc/vector-size-32-2.c | 106 ++++++++++++++ .../gcc.target/powerpc/vector-size-32-3.c | 137 ++++++++++++++++++ .../gcc.target/powerpc/vector-size-32-4.c | 137 ++++++++++++++++++ .../gcc.target/powerpc/vector-size-32-5.c | 137 ++++++++++++++++++ .../gcc.target/powerpc/vector-size-32-6.c | 137 ++++++++++++++++++ .../gcc.target/powerpc/vector-size-32-7.c | 31 ++++ 7 files changed, 791 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c new file mode 100644 index 00000000000..fd1e2decea7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c @@ -0,0 +1,106 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 double elements. */ + +typedef double vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvadddp, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvsubdp, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_multiply (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvmuldp, 1 stxvp. */ + *dest = *a * *b; +} + +void +test_divide (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvdivdp, 1 stxvp. */ + *dest = *a / *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvnegdp, 1 stxvp. */ + *dest = - *a; +} + +void +test_fma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmadd{a,m}dp, 1 stxvp. */ + *dest = (*a * *b) + *c; +} + +void +test_fms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmsub{a,m}dp, 1 stxvp. */ + *dest = (*a * *b) - *c; +} + +void +test_nfma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmadddp, 1 stxvp. */ + *dest = -((*a * *b) + *c); +} + +void +test_nfms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmsubdp, 1 stxvp. */ + *dest = -((*a * *b) - *c); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 21 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 9 } } */ +/* { dg-final { scan-assembler-times {\mxvadddp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvdivdp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmadd.dp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmsub.dp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmuldp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnegdp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmadd.dp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmsub.dp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvsubdp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c new file mode 100644 index 00000000000..eccc9c7aabf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c @@ -0,0 +1,106 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 8 float elements. */ + +typedef float vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvaddsp, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvsubsp, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_multiply (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvmulsp, 1 stxvp. */ + *dest = *a * *b; +} + +void +test_divide (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvdivsp, 1 stxvp. */ + *dest = *a / *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvnegsp, 1 stxvp. */ + *dest = - *a; +} + +void +test_fma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmadd{a,m}sp, 1 stxvp. */ + *dest = (*a * *b) + *c; +} + +void +test_fms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmsub{a,m}sp, 1 stxvp. */ + *dest = (*a * *b) - *c; +} + +void +test_nfma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmaddsp, 1 stxvp. */ + *dest = -((*a * *b) + *c); +} + +void +test_nfms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmsubsp, 1 stxvp. */ + *dest = -((*a * *b) - *c); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 21 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 9 } } */ +/* { dg-final { scan-assembler-times {\mxvaddsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvdivsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmadd.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmsub.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmulsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnegsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmadd.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmsub.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvsubsp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c new file mode 100644 index 00000000000..b1952b046f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef long long vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vaddudm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubudm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 vnegd, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvaddudm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvnegd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubudm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c new file mode 100644 index 00000000000..110292bb4df --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef int vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vadduwm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubuwm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 vnegw, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvadduwm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvnegw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubuwm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c new file mode 100644 index 00000000000..8921b04c468 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef short vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vadduhm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubuhm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 1 xxspltib, 2 vsubuhm, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvadduhm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubuhm\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c new file mode 100644 index 00000000000..a905e6b0a31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef unsigned char vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vaddubm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsububm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 1 xxspltib, 2 vsububm, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvaddubm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsububm\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c new file mode 100644 index 00000000000..a6e8582ba4f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether we can load vector pair constants into registers without using + a load instruction. */ + +typedef double vectype_t __attribute__((__vector_size__(32))); + +void +zero (vectype_t *p) +{ + *p = (vectype_t) { 0.0, 0.0, 0.0, 0.0 }; +} + +void +one (vectype_t *p) +{ + *p = (vectype_t) { 1.0, 1.0, 1.0, 1.0 }; +} + +void +mixed (vectype_t *p) +{ + *p = (vectype_t) { 0.0, 0.0, 1.0, 1.0 }; +} + +/* { dg-final { scan-assembler-not {\mp?lxvpx?\M} } } */ +/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ -- 2.41.0 -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meissner@linux.ibm.com