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* PR111754
@ 2023-11-28  7:56 juzhe.zhong
  2023-11-28  8:43 ` PR111754 Jakub Jelinek
  0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2023-11-28  7:56 UTC (permalink / raw)
  To: gcc-patches; +Cc: richard.sandiford, prathamesh.kulkarni

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Hi, there is a regression in RISC-V caused by this patch:

FAIL: gcc.dg/vect/pr111754.c -flto -ffat-lto-objects  scan-tree-dump optimized "return { 0.0, 9.0e\\+0, 0.0, 0.0 }"
FAIL: gcc.dg/vect/pr111754.c scan-tree-dump optimized "return { 0.0, 9.0e\\+0, 0.0, 0.0 }"

I have checked the dump is :
F foo (F a, F b)
{
  <bb 2> [local count: 1073741824]:
  <retval> = { 0.0, 9.0e+0, 0.0, 0.0 };
  return <retval>;

}

The dump IR seems reasonable to me.
I wonder whether we should walk around in RISC-V backend to generate the same IR as ARM SVE ?
Or we should adjust the test ?

Thanks.


juzhe.zhong@rivai.ai

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-11-28  9:12 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-28  7:56 PR111754 juzhe.zhong
2023-11-28  8:43 ` PR111754 Jakub Jelinek
2023-11-28  8:57   ` [PATCH] testsuite: Fix up pr111754.c test Jakub Jelinek
2023-11-28  9:12     ` Richard Biener

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