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Tue, 28 Nov 2023 15:41:05 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2B57E5805F; Tue, 28 Nov 2023 15:41:05 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 723DE5805A; Tue, 28 Nov 2023 15:41:04 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.83.136]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Tue, 28 Nov 2023 15:41:04 +0000 (GMT) Date: Tue, 28 Nov 2023 10:41:02 -0500 From: Michael Meissner To: "Kewen.Lin" Cc: Michael Meissner , Ajit Agarwal , gcc-patches , David Edelsohn , Segher Boessenkool , Peter Bergner Subject: Re: [PATCH v2] rs6000: Add new pass for replacement of contiguous addresses vector load lxv with lxvp Message-ID: Mail-Followup-To: Michael Meissner , "Kewen.Lin" , Ajit Agarwal , gcc-patches , David Edelsohn , Segher Boessenkool , Peter Bergner References: <629b1028-7f4d-aca1-e6d4-c9fbe9e0e2dc@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <629b1028-7f4d-aca1-e6d4-c9fbe9e0e2dc@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: WydfttvVLVp4-0TwmKqmiJM9OoPaXBm3 X-Proofpoint-GUID: g-8Y7opDyzyDgYv2Yrdyd1FhX8hcl0jd Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-28_17,2023-11-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 mlxlogscore=837 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311280125 X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 28, 2023 at 05:44:43PM +0800, Kewen.Lin wrote: > on 2023/11/28 15:05, Michael Meissner wrote: > > I tried using this patch to compare with the vector size attribute patch I > > posted. I could not build it as a cross compiler on my x86_64 because the > > assembler gives the following error: > > > > Error: operand out of domain (11 is not a multiple of 2) for > > std_stacktrace-elf.o. If you look at the assembler, it has combined a lxvp 11 > > and lxvp 12 into: > > > > lxvp 11,0(9) > > > > The powerpc architecture requires that registers that are loaded with load > > vector pair and stored with store vector point instructions only load/store > > even/odd register pairs, and not odd/even pairs. Unfortunately, it will mean > > that this optimization will match less often. > > > > Yes, the current implementation need some refinements, as comments in [1]: > > > Besides, it seems a bad idea to put this pass after reload? as register allocation > > finishes, this pairing has to be restricted by the reg No. (I didn't see any > > checking on the reg No. relationship for paring btw.) > > > > Looking forward to the comments from Segher/David/Peter/Mike etc. > > I wonder if we should consider running such pass before reload instead. > > [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-November/638070.html > > BR, > Kewen If I add code to check if the target register is even, then the following fails: /home/meissner/fsf-src/work148-ajit/libquadmath/math/erfq.c: In function ‘erfcq’: /home/meissner/fsf-src/work148-ajit/libquadmath/math/erfq.c:943:1: error: insn does not satisfy its constraints: 943 | } | ^ (insn 1087 1939 1088 66 (set (reg/v:KF 74 10 [orig:643 y ] [643]) (fma:KF (reg/v:KF 64 0 [orig:153 z ] [153]) (reg/v:KF 65 1 [orig:639 y ] [639]) (reg:KF 76 12 [orig:642 MEM[(const _Float128 *)p_276 + 16B] ] [642]))) "/home/meissner/fsf-src/work148-ajit/libquadmath/math/erfq.c":112:9 1004 {fmakf4_hw} (expr_list:REG_DEAD (reg/v:KF 65 1 [orig:639 y ] [639]) (nil))) In particular, the IEEE 128-bit arithmetic functions require Altivec registers. So we would need to make sure the new insns all meet their constraints. I tend to think that it would be desirable to do it before reload. But then we will need to check if extra moves are generated. I suspect we will need Peter's patch to allow 128-bit types that are subregs of OOmode. I.e., the code generated would change: (set (reg:MODE1 tmp-reg) (mem ...+8)) (set (reg:MODE2 tmp-reg+1) (mem ...)) to: (set (reg:OO vp-reg) (mem ...)) (set (reg:MODE1 tmp-reg) (subreg:MODE1 (reg:OO vp-reg 0))) (set (reg:MODE2 tmp-reg+1) (subreg:MODE2 (reg:OO vp-reg 16))) Note, I may have the offsets and register numbers backwards in terms of endian. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meissner@linux.ibm.com