From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 0A89038582B6 for ; Mon, 18 Dec 2023 20:16:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0A89038582B6 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0A89038582B6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702930562; cv=none; b=Gmrk1IhxcIirY4yRDxmor6rq2PW4gFFwkxCiHP0/rH/wj9soZSRAZpjbdVN42+80warIP16y12Fwdyty+hmZzAwhhiSqP4oGA6W9J2w6YYthUqJyPG3apAemDWlhZYCWgVJhmdrDz8VXEgmWjwff9diRZfvFgP3VdK3QEf2+82Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702930562; c=relaxed/simple; bh=0Qx0SGtOMMP/HZ0ihxNrP1XfZHzuIcWvuG5UTtBqNZ0=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=kCPaHNv7xXQ6czznUU0I8VpVZGkQJgH8NzkmCBeJov6Ee2DHpeDynaBzmMNaC18xsOyoAcHiGGALlmvB/yCwgeoE2bEAmuD9LcSyCL1Qg9eaV6iPugptdBaJ81Q8d/ez9FLPgaXwi1uFfk1zW+aLB1VWeKD+2R6vaOHnWj/eEDQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1702930560; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SZ4YgblFcm1GS2NhIPZsi3Yi2dTjybWcP79ixFozQdU=; b=Dfe+11djoqis+6nnG/vWbz7jDyQyBQAkc8cy4nPDUMOLx6hn/AK/gpA7r5REU2kIGQOy30 s1Rr4WJ/QJwTehWTJD2fMADWdqZPlU479nboRcYq5B4zDK3MU1R12fuTBk1E7FrZhQiox5 1gppHURE+XcvcMazdD71R8k2GUhPcoI= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-510-67hzhUE-OEufPIbMGOsiMw-1; Mon, 18 Dec 2023 15:15:58 -0500 X-MC-Unique: 67hzhUE-OEufPIbMGOsiMw-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id D236A38562CD; Mon, 18 Dec 2023 20:15:57 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.92]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1C85E492BC6; Mon, 18 Dec 2023 20:15:56 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 3BIKFrxB1301364 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 18 Dec 2023 21:15:54 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 3BIKFp7L1301363; Mon, 18 Dec 2023 21:15:51 +0100 Date: Mon, 18 Dec 2023 21:15:51 +0100 From: Jakub Jelinek To: Xi Ruoyao Cc: Jeff Law , gcc-patches@gcc.gnu.org, chenglulu , i@xen0n.name, xuchenghua@loongson.cn, c@jia.je Subject: Re: [PATCH] middle-end: Call negate_rtx instead of simplify_gen_unary expanding rotate shift [PR113033] Message-ID: Reply-To: Jakub Jelinek References: <20231218134251.1513432-1-xry111@xry111.site> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Dec 19, 2023 at 04:01:52AM +0800, Xi Ruoyao wrote: > On Mon, 2023-12-18 at 18:45 +0100, Jakub Jelinek wrote: > > On Tue, Dec 19, 2023 at 12:48:46AM +0800, Xi Ruoyao wrote: > > > > > gcc/ChangeLog: > > > > > > > > > > PR middle-end/113033 > > > > > * expmed.cc (expand_shift_1): When expanding rotate shift, call > > > > > negate_rtx instead of simplify_gen_unary (NEG, ...). > > > > > > > The key difference being that using negate_rtx will go through the > > > > expander which knows how to synthesize negation whereas > > > > simplify_gen_unary will just generate a (neg ...) and assume it matches > > > > something in the backend, right? > > > > > > For PR113033 the key difference (to me) is negate_rtx emits an insn to > > > set a new pseudo reg to -x.  So the result will be > > > > > > (set (reg:SI 81) (neg:SI (reg:SI 80))) > > > > > > then > > > > > > (and (reg:SI 81) (const_int 31)) > > > > > > instead of a consolidated > > > > > > (and:SI (neg:SI (reg:SI IN)) (const_int 63)) > > > > > > AFAIK no backends have an instruction doing "negate an operand then and > > > bitwisely". > > > > Can you explain why it doesn't work as is though? > > I mean, expand_shift_1 with that (and (neg (reg ...)) (const_int ...)) > > should try to legitimize the operand (e.g. in maybe_legitimize_operand > > -> force_operand and force_operand should be able to deal with that, > > AND is binary op, so it recurses on the 2 operands and NEG is UNARY_P, > > so the recursion should deal with that if it is not general_operand. > > It happens with vector left rotate: > > V test (V a, int x) > { > int _1; > V _4; > > [local count: 1073741824]: > _1 = x_2(D) & 31; > _4 = a_3(D) r<< _1; > return _4; > > } > > Here V is in V4SImode. With other_amount = (and (neg (reg 85)) > (const_int 31)), we end up calling > > expand_shift_1 ( > code = RSHIFT_EXPR, > mode = V4SImode, > shifted = (reg:V4SI 82), > amount = (and:SI (neg:SI (reg:SI 85)) (const_int 31)), > target = (reg:V4SI 84), > unsignedp = true, > may_fail = false) > > It then calls > > expand_binop ( > mode = V4SImode, > lshr_optab, > op0 = (reg:V4SI 82), > op1 = (and:SI (neg:SI (reg:SI 85)) (const_int 31)), > target = (reg:V4SI 84), > unsignedp=1, > methods=OPTAB_DIRECT) > > In expand_binop: > > rtx vop1 = expand_vector_broadcast (mode, op1); > > LoongArch backend don't have vec_duplicate (well, broadcasting is > implemented as a special case of vec_init and maybe this is not so > good...), so finally we get: > > vec = rtvec_alloc (n); > for (int i = 0; i < n; ++i) > RTVEC_ELT (vec, i) = op; > rtx ret = gen_reg_rtx (vmode); > emit_insn (GEN_FCN (icode) (ret, gen_rtx_PARALLEL (vmode, vec))); > > here "op" is (and:SI (neg:SI (reg:SI 85)) (const_int 31)), thus it > evaded expansion :(. Then that seems like a bug in the loongarch vec_init pattern(s). Those really don't have a predicate in any of the backends on the input operand, so they need to force_reg it if it is something it can't handle. I've looked e.g. at i386 vec_init and that is exactly what it does, see the various tests + force_reg calls in ix86_expand_vector_init*. Jakub