From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dellerweb.de (dellerweb.de [173.249.48.176]) by sourceware.org (Postfix) with ESMTPS id EBE9C3858D37 for ; Mon, 18 Mar 2024 00:47:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EBE9C3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=parisc-linux.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=parisc-linux.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EBE9C3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=173.249.48.176 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710722876; cv=none; b=kTgriayMQBGEbiwxV+ypaD7NgwwFy4kPTQ+JRFbCpNriSsTp+eOOO73tqDLuP3FWlNKJ2rW+kNRSNShrh+ZzAyZTPceJNYLISH7R6LvBb0LBsGRYM9MnrViCjDfFQCT+Mu4eO31APZ7FBN6SaLxgw+H4Aic5M97c+GCP13ZEHes= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710722876; c=relaxed/simple; bh=tViXBMZfls13TdWHtNYn/5fkxl3jHFChX7S5607cKAY=; h=Date:From:To:Subject:Message-ID:MIME-Version; b=OvdmfP41l1Ldacx7sUR2LKsv0ft2BzRc7+JBNByRzK0c+TQ/mgwCRnWHsWm3JlvTkvXV1rHKFZRxmsBOzW2rzi/a0QAaIPpmSGreV8eVa7XaxPF30ub87R0a6GVygf+PgnX6HzyvCi23HzEjEbrncG7RblVF4IXF1szIutgKgu8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mx3210.localdomain (bras-base-otwaon0906w-grc-15-142-126-188-251.dsl.bell.ca [142.126.188.251]) by dellerweb.de (Postfix) with ESMTPSA id 70741160027F; Mon, 18 Mar 2024 01:47:53 +0100 (CET) Received: by mx3210.localdomain (Postfix, from userid 1000) id C0B1C22011C; Mon, 18 Mar 2024 00:47:51 +0000 (UTC) Date: Mon, 18 Mar 2024 00:47:51 +0000 From: John David Anglin To: GCC Patches Subject: [committed] hppa: Improve handling of REG+D addresses when generating PA 2.0 code Message-ID: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="9C985zSU9UjgKtPH" Content-Disposition: inline X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --9C985zSU9UjgKtPH Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Tested on hppa-unknown-linux-gnu. Committed to trunk. Dave --- hppa: Improve handling of REG+D addresses when generating PA 2.0 code In looking at PR 112415, it became clear that improvements could be made in the handling of loads and stores using REG+D addresses. A change in 2002 conflated two issues: 1) We can't generate insns with 14-bit displacements before reload completes when generating PA 1.x code since floating-point loads and stores only support 5-bit offsets in PA 1.x. 2) The GNU ELF 32-bit linker lacks relocation support for PA 2.0 floating point instructions with 14-bit displacements. These relocations affect instructions with symbolic references. The result of the change was to block creation of PA 2.0 instructions with 14-bit REG_D displacements for SImode, DImode, SFmode and DFmode on the GNU linux target before reload. This was unnecessary as these instructions don't need relocation. This change revise the INT14_OK_STRICT define to allow creation of instructions with 14-bit REG+D addresses before reload when generating PA 2.0 code. 2024-03-17 John David Anglin gcc/ChangeLog: PR rtl-optimization/112415 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition for symbolic memory operands. (pa_legitimate_address_p): Revise LO_SUM condition. * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move comment about GNU linker to predicates.md. * config/pa/predicates.md (floating_point_store_memory_operand): Revise condition for symbolic memory operands. Update comment. diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc index 129289f8e62..d7666103de8 100644 --- a/gcc/config/pa/pa.cc +++ b/gcc/config/pa/pa.cc @@ -2039,7 +2039,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mo= de, rtx scratch_reg) op1 =3D replace_equiv_address (op1, scratch_reg); } } - else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode= )) + else if (((TARGET_ELF32 || !TARGET_PA_20) + && symbolic_memory_operand (op1, VOIDmode)) || IS_LO_SUM_DLT_ADDR_P (XEXP (op1, 0)) || IS_INDEX_ADDR_P (XEXP (op1, 0))) { @@ -2088,7 +2089,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mo= de, rtx scratch_reg) op0 =3D replace_equiv_address (op0, scratch_reg); } } - else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode= )) + else if (((TARGET_ELF32 || !TARGET_PA_20) + && symbolic_memory_operand (op0, VOIDmode)) || IS_LO_SUM_DLT_ADDR_P (XEXP (op0, 0)) || IS_INDEX_ADDR_P (XEXP (op0, 0))) { @@ -11032,18 +11040,22 @@ pa_legitimate_address_p (machine_mode mode, rtx x= , bool strict, code_helper) && (strict ? STRICT_REG_OK_FOR_BASE_P (y) : REG_OK_FOR_BASE_P (y))) { + y =3D XEXP (x, 1); + /* Needed for -fPIC */ if (mode =3D=3D Pmode - && GET_CODE (XEXP (x, 1)) =3D=3D UNSPEC) + && GET_CODE (y) =3D=3D UNSPEC) return true; =20 - if (!INT14_OK_STRICT - && (strict || !(reload_in_progress || reload_completed)) + /* Before reload, we need support for 14-bit floating + point loads and stores, and associated relocations. */ + if ((TARGET_ELF32 || !INT14_OK_STRICT) + && !reload_completed && mode !=3D QImode && mode !=3D HImode) return false; =20 - if (CONSTANT_P (XEXP (x, 1))) + if (CONSTANT_P (y)) return true; } return false; diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 7abaeae269e..403f16c5cb5 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -828,19 +828,8 @@ extern int may_call_alloca; =20 /* Nonzero if 14-bit offsets can be used for all loads and stores. This is not possible when generating PA 1.x code as floating point - accesses only support 5-bit offsets. Note that we do not forbid - the use of 14-bit offsets prior to reload. Instead, we use secondary - reloads to fix REG+D memory addresses for floating-point accesses. - - FIXME: the GNU ELF linker clobbers the LSB of the FP register number - in PA 2.0 floating-point insns with long displacements. This is - because R_PARISC_DPREL14WR and other relocations like it are not - yet supported by GNU ld. For now, we reject long displacements - on this target. */ - -#define INT14_OK_STRICT \ - (TARGET_SOFT_FLOAT \ - || (TARGET_PA_20 && !TARGET_ELF32 && !TARGET_ELF64)) + accesses only support 5-bit offsets. */ +#define INT14_OK_STRICT (TARGET_SOFT_FLOAT || TARGET_PA_20) =20 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md index 3bd3a7c212f..50dffa1138c 100644 --- a/gcc/config/pa/predicates.md +++ b/gcc/config/pa/predicates.md @@ -331,12 +331,16 @@ && !IS_INDEX_ADDR_P (XEXP (op, 0))); }) =20 -;; True iff the operand OP can be used as the destination operand of -;; a floating point store. This also implies the operand could be used as +;; True iff the operand OP can be used as the destination operand of a +;; floating point store. This also implies the operand could be used as ;; the source operand of a floating point load. LO_SUM DLT and indexed -;; memory operands are not allowed. Symbolic operands are accepted if -;; INT14_OK_STRICT is true. We accept reloading pseudos and other memory -;; operands. +;; memory operands are not allowed. Symbolic operands are accepted for +;; PA 2.0 when TARGET_ELF32 is not true. We accept reloading pseudos +;; and other memory; operands. + +;; FIXME: The GNU ELF32 linker clobbers the LSB of the FP register number +;; in PA 2.0 {fldw,fstw} insns with long displacements. This is because +;; R_PARISC_DPREL14WR and other relocations like it are not supported. =20 (define_predicate "floating_point_store_memory_operand" (match_code "reg,mem") @@ -362,7 +366,8 @@ return false; =20 return ((reload_in_progress || memory_address_p (mode, XEXP (op, 0))) - && (INT14_OK_STRICT || !symbolic_memory_operand (op, VOIDmode)) + && !((TARGET_ELF32 || !TARGET_PA_20) + && symbolic_memory_operand (op, VOIDmode)) && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0)) && !IS_INDEX_ADDR_P (XEXP (op, 0))); }) --9C985zSU9UjgKtPH Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEnRzl+6e9+DTrEhyEXb/Nrl8ZTfEFAmX3jzEACgkQXb/Nrl8Z TfEM9A//fbCNZwDnU7Cr0l1PIDGzugMdj+QpZxd9nMBKT1szDmgDeYSFca4oLLTV R68ZOGezWxKlLcgtR2dmBwB5duglK92aJgF6V5KpZGfmas659oZE2E/lOad0lGTq tYWeZWnCm/yeyAwXbH9dp0fQKzVLhsR34IFQoaC0hUd0kPIj49FtX5aSHAKau1IP 3sdUMAPrL6zaTpWR5YoVwOQbXbVqASiPBE+RPyoeG6+thaZvLaECOvt3kKCGxmE7 Aatz3jM2L1icNvgiJS+eYXMYUj+i49JyouleLsaDkqYLiXs1+bjYdWGHNpoNsCC1 YGxK+PDxKK+Z1/e9cupaUnil56Yw4NIS5UOvxuy4A5afP0arw0Z42E6bfECf8ZEl SofwVu1hae+feGqQvdSoABrddma54tNX2qDV3WhmK/rcTBA+yMTZdN5Php44GFtU wUfVfWD4B5tQW+mQPcRUZ5shoKVeh7L6oi20IXBgeIty5ds1/j2WLVtVePF5mnvV CdLpp85sn+DfNfRfyqQClyLloiWDl0m7M7Z8Ib6XQ6p1nTZXRE6o/03/9HWckmfF fRlXKYjIQX8lgj14XX6zwtgoChC3Gr5pRsrtkW/gIqW2djW/6xZOmsWLfiXd8CSB mHXo7maim77cE2dqjPZ+GPl0wHGl9v6gM7ZyjZ+TYsZj+7zcA80= =wmXu -----END PGP SIGNATURE----- --9C985zSU9UjgKtPH--