From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id A4A1C385841F for ; Thu, 11 Apr 2024 09:08:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A4A1C385841F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A4A1C385841F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712826496; cv=none; b=xwS8tLK9TfRKgplRpWZPvvgHc+dulPqB+dpnMsZtZ6/9vlwNsnUdOu0b2grOh+WPjvY3rWfEAhsc2XAC9xEw7FG3m8oNqeVwCu5JQi0CG/6oVvV+ukDziz9borLtA39bqd1lIk8EMqypKcvMNaKL2FoOEkee1iFanfcO17NfINs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712826496; c=relaxed/simple; bh=o5So5ttc6x54ALvUR9foZH2UdMJv5qLV16xq03lewdM=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=k3M4bkqeCgKDNnhh7cNnq5YxfQYvRPXsiBhnBWJFLRqKfR1ETVKJd3Tq0jS9vsCwTMfFF/YOiJO120QhMAM3v80wap1S7hsLVHnc7c2pIW+CaQm8LwE2cQMYRFGU2OCOcX8phqdnJhPkJvD+27a1ebB3R33I6TEWd06I1pJYmDA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1712826494; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type; bh=pJ/P8rLFU8KnJIWtc0xxzUiO0SqlnPjwHh8hTfgU02g=; b=OSz3LVXcDcjcUfCernv+9fGnHN2OspBEGgGBJWyFvBT/NLikwVzJyuGKtD5O3HJALuOkEL R74wkj9rt+PFmczKkxoHnpozU/qyH44O6b/n8hY80UCRdv5x0wyw00SuI3y6N+YaNuapTv noiJ2T1lOdman69T6FMm9ZwVYyzNUVU= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-658-lDYdr16iMRaVnwVAJ7S-BA-1; Thu, 11 Apr 2024 05:08:10 -0400 X-MC-Unique: lDYdr16iMRaVnwVAJ7S-BA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2D767801788; Thu, 11 Apr 2024 09:08:10 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.45.224.14]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A92F196B; Thu, 11 Apr 2024 09:08:09 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 43B97mqk3019206 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Thu, 11 Apr 2024 11:07:48 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 43B97lsE3019205; Thu, 11 Apr 2024 11:07:47 +0200 Date: Thu, 11 Apr 2024 11:07:47 +0200 From: Jakub Jelinek To: Uros Bizjak , Mayshao-oc Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] invoke.texi: Clarify -march=lujiazui Message-ID: Reply-To: Jakub Jelinek MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi! Yesterday I was searching which exact CPUs are affected by the PR114576 wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march= cases which do enable -maes and don't enable -mavx). But when double-checking that against the invoke.texi documentation, that was true for the first 3, but lujiazui said it supported AVX. I was really confused by that, until I found the https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html explanation. So, seems the CPUs do have AVX and F16C but -march=lujiazui doesn't enable those and even activelly attempts to filter those out from the announced CPUID features, in glibc as well as e.g. in libgcc. Thus, I think we should document what actually happens, otherwise users could assume that gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't. Tested on x86_64, ok for trunk? 2024-04-11 Jakub Jelinek * doc/invoke.texi (lujiazui): Clarify that while the CPUs do support AVX and F16C, -march=lujiazui actually doesn't enable those. --- gcc/doc/invoke.texi.jj 2024-04-11 09:26:01.156865894 +0200 +++ gcc/doc/invoke.texi 2024-04-11 10:47:53.457582922 +0200 @@ -34696,8 +34696,10 @@ instruction set support. @item lujiazui ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} +for performance reasons. @item yongfeng ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, Jakub