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Thu, 27 Jun 2024 06:25:18 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AC8B72004B; Thu, 27 Jun 2024 06:25:16 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5251C20040; Thu, 27 Jun 2024 06:25:16 +0000 (GMT) Received: from li-819a89cc-2401-11b2-a85c-cca1ce6aa768.ibm.com (unknown [9.171.76.194]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTPS; Thu, 27 Jun 2024 06:25:16 +0000 (GMT) Date: Thu, 27 Jun 2024 08:25:03 +0200 From: Stefan Schulze Frielinghaus To: Paul Koning Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] Hard register asm constraint Message-ID: References: <20240524091312.209365-1-stefansf@linux.ibm.com> <0701EC44-8E0B-4584-B72F-D4251C902B32@comcast.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DjviV3F9gj7xpZzkfcZnkpJ7YEJspKaa X-Proofpoint-GUID: S42Y7Qt4rMW9SjCxRIXxrqp1r1pTzSV9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-27_02,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 mlxlogscore=533 phishscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406270047 X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Jun 26, 2024 at 11:10:38AM -0400, Paul Koning wrote: > > > > On Jun 26, 2024, at 8:54 AM, Stefan Schulze Frielinghaus wrote: > > > > On Tue, Jun 25, 2024 at 01:02:39PM -0400, Paul Koning wrote: > >> > >> > >>> On Jun 25, 2024, at 12:04 PM, Stefan Schulze Frielinghaus wrote: > >>> > >>> On Tue, Jun 25, 2024 at 10:03:34AM -0400, Paul Koning wrote: > >>>> > >>>>>>> ... > >>>>>>> could be rewritten into > >>>>>>> > >>>>>>> int test (int x, int y) > >>>>>>> { > >>>>>>> asm ("foo %0,%1,%2" : "+{r4}" (x) : "{r5}" (y), "d" (y)); > >>>>>>> return x; > >>>>>>> } > >>>> > >>>> I like this idea but I'm wondering: regular constraints specify what sort of value is needed, for example an int vs. a short int vs. a float. The notation you've shown doesn't seem to have that aspect. > >>> > >>> As Maciej already pointed out the type of the expression should suffice. > >>> My assumption was that an asm can deal with a value as is or its > >>> promoted value. At least for integer values this should be fine and > >>> AFAICS is also the case for simple constraints like "r" which do not > >>> define any mode. I've probably overseen something but which constraint > >>> differentiates between int vs short? However, you have a good point > >>> with this and I should test this more. > >> > >> I thought there was but I may be confused. On the other hand, there definitely are (machine dependent) constraints that distinguish, say, float from integer registers; pdp11 is an example. If you were to use an "a" constraint, that means a floating point register and the compiler will detect attempts to pass non-float operands ("Inconsistent operand constraints..."). > >> > >> I see that the existing "register int ..." syntax appears to check that the register is the right type for the data type given for it, so for example on pdp11, > >> > >> register int ac1 asm ("ac1") = i; > >> > >> fails ("register ... isn't suitable for data type"). I assume your new syntax would perform the same check and produce roughly the same error message. You might verify that. On pdp11, trying to use, for example, "r0" for a float, or "ac0" for an int, would produce that error. > > > > Right, so far I don't error out here which I will change. It basically > > results in bit casting floats to ints currently. > > That would be bad. For one thing, a PDP11 float doesn't fit in an integer register. > > That also brings up another point (which applies to more mainstream targets as well): for data types that require multiple registers, say a register pair for a double length value, how is that handled? One possible answer is to reject that. Another would be to load a register pair. > > This case applies to a "long int" on pdp11, or 32 bit MIPS, and probably a bunch of others. Absolutely, also on mainstream targets you could think of 128-bit integers or long doubles which typically don't fit in (single) GPRs. I should definitely add error handling for this. Similar, I don't error out for non-primitive data types. I will give register pairs a try. Thanks for all your comments so far :) Cheers, Stefan