From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id F18CD383D831 for ; Thu, 9 Jun 2022 19:38:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F18CD383D831 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 069AF12408AC; Thu, 9 Jun 2022 19:38:42 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, "Kewen.Lin" , Segher Boessenkool Subject: [PATCH] rs6000: Delete FP_ISA3 Date: Thu, 9 Jun 2022 19:38:33 +0000 Message-Id: X-Mailer: git-send-email 1.8.3.1 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jun 2022 19:38:45 -0000 FP_ISA3 is exactly the same as SFDF, just a less obvious name. So, let's delete it. Tested, committed, the works. Segher 2022-06-09 Segher Boessenkool * config/rs6000/rs6000.md (FP_ISA3): Delete. (float2): Rename to... (float2): ... this. Adjust. (*float2_internal): Rename to... (*float2_internal): ... this. Adjust. (floatuns2): Rename to... (floatuns2): ... this. Adjust. (*floatuns2_internal): Rename to... (*floatuns2_internal): ... this. Adjust. --- gcc/config/rs6000/rs6000.md | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1c125f07e895..c55ee7e171a3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -619,9 +619,6 @@ (define_mode_iterator FLOAT128 [(KF "TARGET_FLOAT128_TYPE") (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) -; Iterator for ISA 3.0 supported floating point types -(define_mode_iterator FP_ISA3 [SF DF]) - ; Which isa is needed for those float instructions? (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) @@ -6012,9 +6009,9 @@ (define_insn_and_split "*floatunssidf2_internal" ;; the vector registers, rather then loading up a GPR, doing a sign/zero ;; extension and then a direct move. -(define_expand "float2" - [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") - (float:FP_ISA3 +(define_expand "float2" + [(parallel [(set (match_operand:SFDF 0 "vsx_register_operand") + (float:SFDF (match_operand:QHI 1 "input_operand"))) (clobber (match_scratch:DI 2)) (clobber (match_scratch:DI 3)) @@ -6025,9 +6022,9 @@ (define_expand "float2" operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]); }) -(define_insn_and_split "*float2_internal" - [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa") - (float:FP_ISA3 +(define_insn_and_split "*float2_internal" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa,wa,wa") + (float:SFDF (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=v,wa,v")) (clobber (match_scratch:DI 3 "=X,r,X")) @@ -6061,14 +6058,14 @@ (define_insn_and_split "*float2_internal" emit_insn (gen_extenddi2 (di, tmp)); } - emit_insn (gen_floatdi2 (result, di)); + emit_insn (gen_floatdi2 (result, di)); DONE; } [(set_attr "isa" "p9v,*,p9v")]) -(define_expand "floatuns2" - [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") - (unsigned_float:FP_ISA3 +(define_expand "floatuns2" + [(parallel [(set (match_operand:SFDF 0 "vsx_register_operand") + (unsigned_float:SFDF (match_operand:QHI 1 "input_operand"))) (clobber (match_scratch:DI 2)) (clobber (match_scratch:DI 3))])] @@ -6078,9 +6075,9 @@ (define_expand "floatuns2" operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]); }) -(define_insn_and_split "*floatuns2_internal" - [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa") - (unsigned_float:FP_ISA3 +(define_insn_and_split "*floatuns2_internal" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa,wa,wa") + (unsigned_float:SFDF (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=v,wa,wa")) (clobber (match_scratch:DI 3 "=X,r,X"))] @@ -6107,7 +6104,7 @@ (define_insn_and_split "*floatuns2_internal" } } - emit_insn (gen_floatdi2 (result, di)); + emit_insn (gen_floatdi2 (result, di)); DONE; } [(set_attr "isa" "p9v,*,p9v")]) -- 1.8.3.1