From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 26E25383236D for ; Mon, 14 Nov 2022 18:51:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 26E25383236D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from [10.10.3.121] (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTPS id 80B3F40D403E; Mon, 14 Nov 2022 18:51:37 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 80B3F40D403E Date: Mon, 14 Nov 2022 21:51:37 +0300 (MSK) From: Alexander Monakov To: "Joshi, Tejas Sanjay" cc: "gcc-patches@gcc.gnu.org" , "honza.hubicka@gmail.com" , "Kumar, Venkataramanan" Subject: Re: [PATCH][X86_64] Separate znver4 insn reservations from older znvers In-Reply-To: Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022, Joshi, Tejas Sanjay wrote: > [Public] > > Hi, Hi. I'm still waiting for feedback on fixes for existing models: https://inbox.sourceware.org/gcc-patches/5ae6fc21-edc6-133-aee2-a41e16eb5b7@ispras.ru/T/#t did you have a chance to look at those? > PFA the patch which adds znver4 instruction reservations separately from older > znver versions: > * This also models separate div, fdiv and ssediv units accordingly. Why are you modeling 'fdiv' and 'ssediv' separately? When preparing the above patches, I checked that x87 and SSE divisions use the same hardware unit, and I don't see a strong reason to artificially clone it in the model. (integer divider is a separate unit from the floating-point divider) > * Does not blow-up the insn-automata.cc size (it grew from 201502 to 206141 for me.) > * The patch successfully builds, bootstraps, and passes make check. > * I have also run spec, showing no regressions for 1-copy 3-iteration runs. However, I observe 1.5% gain for 507.cactuBSSN_r. I have a question on AVX512 modeling in your patch: > +;; AVX instructions > +(define_insn_reservation "znver4_sse_log" 1 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "sselog,sselog1") > + (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fpu") > + > +(define_insn_reservation "znver4_sse_log_evex" 1 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "sselog,sselog1") > + (and (eq_attr "mode" "V16SF,V8DF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3") > + This is an AVX512 instruction, and you're modeling that it occupies two ports at once and thus has half throughput, but later in the AVX512 section: > +;; AVX512 instructions > +(define_insn_reservation "znver4_sse_mul_evex" 3 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssemul") > + (and (eq_attr "mode" "V16SF,V8DF") > + (eq_attr "memory" "none")))) > + "znver4-double,znver4-fpu0|znver4-fpu3") none of the instructions are modeled this way. If that's on purpose, can you add a comment? It's surprising, since generally AVX512 has half throughput compared to AVX256 on Zen 4, but the model doesn't seem to reflect that. Alexander