From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id BEDD93AA9920; Fri, 18 Jun 2021 15:02:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BEDD93AA9920 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: 7ZFRLyk1yhfTOC5yCNWtN9BDCbwNHat7/wJOCLr/Ju2VTZpmaEAvnsfF6BvpIL6MQQalOhr4fk QzmzUAKvIxJIPgWQkCf25ZoXKckjlFC+MwLQnI2iTGxXazBbxqYSxm5av0gW5BKoGuQeUaLPB+ gF/Ol9+sjrV2bXZhpoiUIknjBXfZsgxQjf/+OHu7tCoBPJXkP8W7emGquokaPfyQ905MJDsGnZ qMkGdddxvMnxnT8sRN1FqDo2bHD2B9NroiWFaWSv3TN7nqxzW6P1wNuQtmsnlk+Yzw7+9ZvelD +Zk= X-IronPort-AV: E=Sophos;i="5.83,284,1616486400"; d="scan'208";a="62748255" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 18 Jun 2021 07:02:01 -0800 IronPort-SDR: AXtozxgqWMkxkPEWLuOlfmFXlJCEyN8YHGqrcSHgnHrPogu9ocnjjMojYzoUi9EE1u5RXLXqNM 7VVtqBw1e+J6awU3VJn7AZnXCSniZacfCWsSCp7RB5ePADSD0H4dR80lePK6nIMIT7rq0OS79g eYD8FYN2E8CjuuXMZTPb+Sy7L/+Eg/LZ0vpvo7MptGfvIh7oyTb1UBi96kmWcKBkyzwLmUAjLt nhskjC1p82Tnd2gyaVVHbO1RuKefj4eEzI8fUqTMvuSK+BFwdkRAlCL2OVqj+ShYspGQ2arVs/ dF4= Subject: Re: [PATCH 3/5] amdgcn: Add clrsbsi2/clrsbdi2 implementation To: Julian Brown , CC: , Tobias Burnus , Jakub Jelinek , Thomas Schwinge References: <0ec87e2fb22898e2578c4deacfce958b92c6d94f.1624025450.git.julian@codesourcery.com> From: Andrew Stubbs Message-ID: Date: Fri, 18 Jun 2021 16:01:55 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <0ec87e2fb22898e2578c4deacfce958b92c6d94f.1624025450.git.julian@codesourcery.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) To svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, NICE_REPLY_A, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Jun 2021 15:02:05 -0000 On 18/06/2021 15:19, Julian Brown wrote: > This patch adds an open-coded implementation of the clrsb2 > (count leading redundant sign bit) standard names using the GCN flbit_i* > instructions for SImode and DImode. Those don't count exactly as we need, > so we need a couple of other instructions to fix up the result afterwards. > > These patterns are lost from libgcc if we build it for DImode/TImode > rather than SImode/DImode, a change we make in a later patch in this > series. > > I can probably self-approve this, but I'll give Andrew Stubbs a chance > to comment. > > Thanks, > > Julian > > 2021-06-18 Julian Brown > > gcc/ > * config/gcn/gcn.md (UNSPEC_FLBIT_INT): New unspec constant. > (s_mnemonic): Add clrsb. > (gcn_flbit_int): Add insn pattern for SImode/DImode. > (clrsb2): Add expander for SImode/DImode. > --- > gcc/config/gcn/gcn.md | 40 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md > index 70655ca4b8b..0fa7f86702e 100644 > --- a/gcc/config/gcn/gcn.md > +++ b/gcc/config/gcn/gcn.md > @@ -81,7 +81,8 @@ > UNSPEC_MOV_FROM_LANE63 > UNSPEC_GATHER > UNSPEC_SCATTER > - UNSPEC_RCP]) > + UNSPEC_RCP > + UNSPEC_FLBIT_INT]) > > ;; }}} > ;; {{{ Attributes > @@ -338,7 +339,8 @@ > [(not "not%b") > (popcount "bcnt1_i32%b") > (clz "flbit_i32%b") > - (ctz "ff1_i32%b")]) > + (ctz "ff1_i32%b") > + (clrsb "flbit_i32%i")]) > > (define_code_attr revmnemonic > [(minus "subrev%i") > @@ -1509,6 +1511,40 @@ > [(set_attr "type" "sop1") > (set_attr "length" "4,8")]) > > +(define_insn "gcn_flbit_int" > + [(set (match_operand:SI 0 "register_operand" "=Sg,Sg") > + (unspec:SI [(match_operand:SIDI 1 "gcn_alu_operand" "SgA, B")] > + UNSPEC_FLBIT_INT))] > + "" > + { > + if (mode == SImode) > + return "s_flbit_i32\t%0, %1"; > + else > + return "s_flbit_i32_i64\t%0, %1"; > + } > + [(set_attr "type" "sop1") > + (set_attr "length" "4,8")]) > + > +(define_expand "clrsb2" > + [(set (match_operand:SI 0 "register_operand" "") > + (clrsb:SI (match_operand:SIDI 1 "gcn_alu_operand" "")))] > + "" > + { > + rtx tmp = gen_reg_rtx (SImode); > + /* FLBIT_I* counts sign or zero bits at the most-significant end of the > + input register (and returns -1 for 0/-1 inputs). We want the number of > + *redundant* bits (i.e. that value minus one), and an answer of 31/63 for > + 0/-1 inputs. We can do that in three instructions... */ > + emit_insn (gen_gcn_flbit_int (tmp, operands[1])); > + emit_insn (gen_uminsi3 (tmp, tmp, > + gen_int_mode (GET_MODE_BITSIZE (mode), > + SImode))); > + /* If we put this last, it can potentially be folded into a subsequent > + arithmetic operation. */ > + emit_insn (gen_subsi3 (operands[0], tmp, const1_rtx)); > + DONE; > + }) > + > ;; }}} > ;; {{{ ALU: generic 32-bit binop > > OK. Andrew