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([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id l12-20020a170903120c00b001785dddc703sm9209218plh.120.2022.10.11.16.14.06 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Oct 2022 16:14:07 -0700 (PDT) Message-ID: Date: Tue, 11 Oct 2022 17:14:05 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Content-Language: en-US To: gcc-patches@gcc.gnu.org References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/11/22 13:31, Palmer Dabbelt wrote: > On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote: >> Hi Christoph, Kito, >> >> On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote: >>> This series provides a cleanup of the current atomics implementation >>> of RISC-V: >>> >>> * PR100265: Use proper fences for atomic load/store >>> * PR100266: Provide programmatic implementation of CAS >>> >>> As both are very related, I merged the patches into one series. >>> >>> The first patch could be squashed into the following patches, >>> but I found it easier to understand the chances with it in place. >>> >>> The series has been tested as follows: >>> * Building and testing a multilib RV32/64 toolchain >>>    (bootstrapped with riscv-gnu-toolchain repo) >>> * Manual review of generated sequences for GCC's atomic builtins API >>> >>> The programmatic re-implementation of CAS benefits from a REE >>> improvement >>> (see PR100264): >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html >>> If this patch is not in place, then an additional extension instruction >>> is emitted after the SC.W (in case of RV64 and CAS for uint32_t). >>> >>> Further, the new CAS code requires cbranch INSN helpers to be present: >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html >> >> I was wondering is this patchset is blocked on some technical grounds. > > There's a v3 (though I can't find all of it, so not quite sure what > happened), but IIUC that still has the same fundamental problems that > all these have had: changing over to the new fence model may by an ABI > break and the split CAS implementation doesn't ensure eventual success > (see Jim's comments).  Not sure if there's other comments floating > around, though, that's just what I remember. Do we have a pointer to the ABI discussion.  I've been meaning to familiarize myself with the issues in this space and that seems like a good place to start given its blocking progress on the atomics. jeff