From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 406453983C54 for ; Tue, 27 Jul 2021 21:06:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 406453983C54 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16RL3kgT022927; Tue, 27 Jul 2021 17:06:44 -0400 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 3a2sepgjus-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 17:06:44 -0400 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16RL2C4m002597; Tue, 27 Jul 2021 21:06:42 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma04wdc.us.ibm.com with ESMTP id 3a235n3gg9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 21:06:42 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16RL6gw540305114 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 27 Jul 2021 21:06:42 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2428328076; Tue, 27 Jul 2021 21:06:42 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1182128065; Tue, 27 Jul 2021 21:06:41 +0000 (GMT) Received: from lexx (unknown [9.171.17.235]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 27 Jul 2021 21:06:40 +0000 (GMT) Message-ID: Subject: Re: [PATCH 46/55] rs6000: Builtin expansion, part 3 From: will schmidt To: Bill Schmidt , gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org Date: Tue, 27 Jul 2021 16:06:39 -0500 In-Reply-To: <7d3846877141b74d4042aec96b9147a7e9d7285c.1623941442.git.wschmidt@linux.ibm.com> References: <7d3846877141b74d4042aec96b9147a7e9d7285c.1623941442.git.wschmidt@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-10.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 2JGTTEfoF9d-rrbDl9OiLKW6bKV99h4o X-Proofpoint-GUID: 2JGTTEfoF9d-rrbDl9OiLKW6bKV99h4o X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-27_14:2021-07-27, 2021-07-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 adultscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 spamscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107270119 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jul 2021 21:06:46 -0000 On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote: > 2021-03-05 Bill Schmidt > Hi, > gcc/ > * config/rs6000/rs6000-call.c (new_cpu_expand_builtin): > Implement. ok > --- > gcc/config/rs6000/rs6000-call.c | 100 ++++++++++++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c > index 754cd46b1c1..ad3e6a4bbe5 100644 > --- a/gcc/config/rs6000/rs6000-call.c > +++ b/gcc/config/rs6000/rs6000-call.c > @@ -14604,6 +14604,106 @@ static rtx > new_cpu_expand_builtin (enum rs6000_gen_builtins fcode, > tree exp ATTRIBUTE_UNUSED, rtx target) > { > + /* __builtin_cpu_init () is a nop, so expand to nothing. */ > + if (fcode == RS6000_BIF_CPU_INIT) > + return const0_rtx; > + > + if (target == 0 || GET_MODE (target) != SImode) > + target = gen_reg_rtx (SImode); > + > +#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB > + tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0); > + /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back > + to a STRING_CST. */ > + if (TREE_CODE (arg) == ARRAY_REF > + && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST > + && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST > + && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0) > + arg = TREE_OPERAND (arg, 0); > + > + if (TREE_CODE (arg) != STRING_CST) > + { > + error ("builtin %qs only accepts a string argument", > + rs6000_builtin_info_x[(size_t) fcode].bifname); > + return const0_rtx; > + } > + > + if (fcode == RS6000_BIF_CPU_IS) > + { > + const char *cpu = TREE_STRING_POINTER (arg); > + rtx cpuid = NULL_RTX; > + for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++) > + if (strcmp (cpu, cpu_is_info[i].cpu) == 0) > + { > + /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */ > + cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM); > + break; > + } ok > + if (cpuid == NULL_RTX) > + { > + /* Invalid CPU argument. */ > + error ("cpu %qs is an invalid argument to builtin %qs", > + cpu, rs6000_builtin_info_x[(size_t) fcode].bifname); > + return const0_rtx; > + } > + > + rtx platform = gen_reg_rtx (SImode); > + rtx tcbmem = gen_const_mem (SImode, > + gen_rtx_PLUS (Pmode, > + gen_rtx_REG (Pmode, TLS_REGNUM), > + GEN_INT (TCB_PLATFORM_OFFSET))); > + emit_move_insn (platform, tcbmem); > + emit_insn (gen_eqsi3 (target, platform, cpuid)); > + } > + else if (fcode == RS6000_BIF_CPU_SUPPORTS) > + { > + const char *hwcap = TREE_STRING_POINTER (arg); > + rtx mask = NULL_RTX; > + int hwcap_offset; > + for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++) > + if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0) > + { > + mask = GEN_INT (cpu_supports_info[i].mask); > + hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id); > + break; > + } > + if (mask == NULL_RTX) > + { > + /* Invalid HWCAP argument. */ > + error ("%s %qs is an invalid argument to builtin %qs", > + "hwcap", hwcap, > + rs6000_builtin_info_x[(size_t) fcode].bifname); > + return const0_rtx; > + } > + > + rtx tcb_hwcap = gen_reg_rtx (SImode); > + rtx tcbmem = gen_const_mem (SImode, > + gen_rtx_PLUS (Pmode, > + gen_rtx_REG (Pmode, TLS_REGNUM), > + GEN_INT (hwcap_offset))); > + emit_move_insn (tcb_hwcap, tcbmem); > + rtx scratch1 = gen_reg_rtx (SImode); > + emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask))); > + rtx scratch2 = gen_reg_rtx (SImode); > + emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx)); > + emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx))); > + } > + else > + gcc_unreachable (); > + > + /* Record that we have expanded a CPU builtin, so that we can later > + emit a reference to the special symbol exported by LIBC to ensure we > + do not link against an old LIBC that doesn't support this feature. */ > + cpu_builtin_p = true; > + > +#else > + warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " > + "capability bits", rs6000_builtin_info_x[(size_t) fcode].bifname); > + This seems OK. It appears to comply with the documentation at least :-) "If GCC was configured to use a GLIBC before 2.23, the built-in function __builtin_cpu_is always returns a 0 and the compiler issues a warning." ok lgtm, thanks -Will > + /* For old LIBCs, always return FALSE. */ > + emit_move_insn (target, GEN_INT (0)); > +#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */ > + > return target; > } >