From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id AF4B9398545E for ; Wed, 18 Aug 2021 20:01:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AF4B9398545E Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 17IJahuB166239; Wed, 18 Aug 2021 16:01:40 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 3ag7bt5pm1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Aug 2021 16:01:39 -0400 Received: from m0098414.ppops.net (m0098414.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 17IJk0Eg191886; Wed, 18 Aug 2021 16:01:39 -0400 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0b-001b2d01.pphosted.com with ESMTP id 3ag7bt5pks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Aug 2021 16:01:39 -0400 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 17IJwJDM017844; Wed, 18 Aug 2021 20:01:38 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma03dal.us.ibm.com with ESMTP id 3ae5fff9c8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Aug 2021 20:01:38 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 17IK1bVY12452704 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Aug 2021 20:01:37 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 163372805C; Wed, 18 Aug 2021 20:01:37 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 57C6028065; Wed, 18 Aug 2021 20:01:36 +0000 (GMT) Received: from Bills-MacBook-Pro.local (unknown [9.211.84.147]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 18 Aug 2021 20:01:36 +0000 (GMT) Reply-To: wschmidt@linux.ibm.com Subject: Re: [PATCH] Move xx* builtins to vsx.md. To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Peter Bergner , Will Schmidt References: From: Bill Schmidt Message-ID: Date: Wed, 18 Aug 2021 15:01:35 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-GB X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tqVXQDWNG1ODOLHBZQYp9sqVwNXVX4PE X-Proofpoint-GUID: ph0r6duQpYWp5hS6hHS88GGvqK_5V9W4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-18_07:2021-08-17, 2021-08-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108180120 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, MEDICAL_SUBJECT, NICE_REPLY_A, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Aug 2021 20:01:51 -0000 Hi Mike, On 8/12/21 11:20 PM, Michael Meissner wrote: > Move xx* builtins to vsx.md. > > I originally posted this patch in May. It needed a slight tune up as the > souces have changed, so I'm reposting it now. > > I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx, > xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since > the XX instructions can take both traditional floating point and Altivec > registers, these built-in functions should be in vsx.md. > > This patch just moves the insns from altivec.md to vsx.md. > > I also moved the VM3 mode iterator and VM3_char mode attribute from altivec.md > to vsx.md, since the only use of these were for the XXBLEND insns. > > I have built little endian power9 compilers, little endian power10 compilers, > and big endian power8 compilers with this patch applied, and there were no > regressions. Can I apply this patch to the master branch? > > Note this patch assumes the previous patch: > > Fix xxeval predicates (PR 99921). > > has been applied. This looks straightforward and fine to me.  Recommend approval... Thanks, Bill > > 2021-08-12 Michael Meissner > > gcc/ > * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md. > (UNSPEC_XXSPLTIW): Move to vsx.md. > (UNSPEC_XXSPLTID): Move to vsx.md. > (UNSPEC_XXSPLTI32DX): Move to vsx.md. > (UNSPEC_XXBLEND): Move to vsx.md. > (UNSPEC_XXPERMX): Move to vsx.md. > (VM3): Move to vsx.md. > (VM3_char): Move to vsx.md. > (xxspltiw_v4si): Move to vsx.md. > (xxspltiw_v4sf): Move to vsx.md. > (xxspltiw_v4sf_inst): Move to vsx.md. > (xxspltidp_v2df): Move to vsx.md. > (xxspltidp_v2df_inst): Move to vsx.md. > (xxsplti32dx_v4si_inst): Move to vsx.md. > (xxsplti32dx_v4sf): Move to vsx.md. > (xxsplti32dx_v4sf_inst): Move to vsx.md. > (xxblend_): Move to vsx.md. > (xxpermx): Move to vsx.md. > (xxpermx_inst): Move to vsx.md. > * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md. > (UNSPEC_XXSPLTIW): Move from altivec.md. > (UNSPEC_XXSPLTID): Move from altivec.md. > (UNSPEC_XXSPLTI32DX): Move from altivec.md. > (UNSPEC_XXBLEND): Move from altivec.md. > (UNSPEC_XXPERMX): Move from altivec.md. > (VM3): Move from altivec.md. > (VM3_char): Move from altivec.md. > (xxspltiw_v4si): Move from altivec.md. > (xxspltiw_v4sf): Move from altivec.md. > (xxspltiw_v4sf_inst): Move from altivec.md. > (xxspltidp_v2df): Move from altivec.md. > (xxspltidp_v2df_inst): Move from altivec.md. > (xxsplti32dx_v4si_inst): Move from altivec.md. > (xxsplti32dx_v4sf): Move from altivec.md. > (xxsplti32dx_v4sf_inst): Move from altivec.md. > (xxblend_): Move from altivec.md. > (xxpermx): Move from altivec.md. > (xxpermx_inst): Move from altivec.md. > --- > gcc/config/rs6000/altivec.md | 197 --------------------------------- > gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++ > 2 files changed, 206 insertions(+), 197 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index fd86c300981..2c73ddea823 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -175,16 +175,10 @@ (define_c_enum "unspec" > UNSPEC_VPEXTD > UNSPEC_VCLRLB > UNSPEC_VCLRRB > - UNSPEC_XXEVAL > UNSPEC_VSTRIR > UNSPEC_VSTRIL > UNSPEC_SLDB > UNSPEC_SRDB > - UNSPEC_XXSPLTIW > - UNSPEC_XXSPLTID > - UNSPEC_XXSPLTI32DX > - UNSPEC_XXBLEND > - UNSPEC_XXPERMX > ]) > > (define_c_enum "unspecv" > @@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI > (KF "FLOAT128_VECTOR_P (KFmode)") > (TF "FLOAT128_VECTOR_P (TFmode)")]) > > -;; Like VM2, just do char, short, int, long, float and double > -(define_mode_iterator VM3 [V4SI > - V8HI > - V16QI > - V4SF > - V2DF > - V2DI]) > - > -(define_mode_attr VM3_char [(V2DI "d") > - (V4SI "w") > - (V8HI "h") > - (V16QI "b") > - (V2DF "d") > - (V4SF "w")]) > - > ;; Map the Vector convert single precision to double precision for integer > ;; versus floating point > (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")]) > @@ -859,170 +838,6 @@ (define_insn "vsdb_" > "vsdbi %0,%1,%2,%3" > [(set_attr "type" "vecsimple")]) > > -(define_insn "xxspltiw_v4si" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > - "xxspltiw %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxspltiw_v4sf" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > -{ > - long value = rs6000_const_f32_to_i32 (operands[1]); > - emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); > - DONE; > -}) > - > -(define_insn "xxspltiw_v4sf_inst" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > - "xxspltiw %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxspltidp_v2df" > - [(set (match_operand:V2DF 0 "register_operand" ) > - (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] > - UNSPEC_XXSPLTID))] > - "TARGET_POWER10" > -{ > - long value = rs6000_const_f32_to_i32 (operands[1]); > - rs6000_emit_xxspltidp_v2df (operands[0], value); > - DONE; > -}) > - > -(define_insn "xxspltidp_v2df_inst" > - [(set (match_operand:V2DF 0 "register_operand" "=wa") > - (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > - UNSPEC_XXSPLTID))] > - "TARGET_POWER10" > - "xxspltidp %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxsplti32dx_v4si" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > -{ > - int index = INTVAL (operands[2]); > - > - if (!BYTES_BIG_ENDIAN) > - index = 1 - index; > - > - emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1], > - GEN_INT (index), operands[3])); > - DONE; > -} > - [(set_attr "type" "vecsimple")]) > - > -(define_insn "xxsplti32dx_v4si_inst" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > - "xxsplti32dx %x0,%2,%3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxsplti32dx_v4sf" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SF 3 "const_double_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > -{ > - int index = INTVAL (operands[2]); > - long value = rs6000_const_f32_to_i32 (operands[3]); > - if (!BYTES_BIG_ENDIAN) > - index = 1 - index; > - > - emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1], > - GEN_INT (index), GEN_INT (value))); > - DONE; > -}) > - > -(define_insn "xxsplti32dx_v4sf_inst" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > - "xxsplti32dx %x0,%2,%3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_insn "xxblend_" > - [(set (match_operand:VM3 0 "register_operand" "=wa") > - (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa") > - (match_operand:VM3 2 "register_operand" "wa") > - (match_operand:VM3 3 "register_operand" "wa")] > - UNSPEC_XXBLEND))] > - "TARGET_POWER10" > - "xxblendv %x0,%x1,%x2,%x3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxpermx" > - [(set (match_operand:V2DI 0 "register_operand" "+wa") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > - (match_operand:V2DI 2 "register_operand" "wa") > - (match_operand:V16QI 3 "register_operand" "wa") > - (match_operand:QI 4 "u8bit_cint_operand" "n")] > - UNSPEC_XXPERMX))] > - "TARGET_POWER10" > -{ > - if (BYTES_BIG_ENDIAN) > - emit_insn (gen_xxpermx_inst (operands[0], operands[1], > - operands[2], operands[3], > - operands[4])); > - else > - { > - /* Reverse value of byte element indexes by XORing with 0xFF. > - Reverse the 32-byte section identifier match by subracting bits [0:2] > - of elemet from 7. */ > - int value = INTVAL (operands[4]); > - rtx vreg = gen_reg_rtx (V16QImode); > - > - emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); > - emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); > - value = 7 - value; > - emit_insn (gen_xxpermx_inst (operands[0], operands[2], > - operands[1], operands[3], > - GEN_INT (value))); > - } > - > - DONE; > -} > - [(set_attr "type" "vecsimple")]) > - > -(define_insn "xxpermx_inst" > - [(set (match_operand:V2DI 0 "register_operand" "+v") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") > - (match_operand:V2DI 2 "register_operand" "v") > - (match_operand:V16QI 3 "register_operand" "v") > - (match_operand:QI 4 "u3bit_cint_operand" "n")] > - UNSPEC_XXPERMX))] > - "TARGET_POWER10" > - "xxpermx %x0,%x1,%x2,%x3,%4" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > (define_expand "vstrir_" > [(set (match_operand:VIshort 0 "altivec_register_operand") > (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] > @@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi" > [(set_attr "type" "vecperm") > (set_attr "isa" "p9v,*")]) > > -(define_insn "xxeval" > - [(set (match_operand:V2DI 0 "register_operand" "=wa") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > - (match_operand:V2DI 2 "register_operand" "wa") > - (match_operand:V2DI 3 "register_operand" "wa") > - (match_operand:QI 4 "u8bit_cint_operand" "n")] > - UNSPEC_XXEVAL))] > - "TARGET_POWER10" > - "xxeval %0,%1,%2,%3,%4" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > (define_expand "vec_unpacku_hi_v16qi" > [(set (match_operand:V8HI 0 "register_operand" "=v") > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 6f6fc0bd835..cacdd0d4cc8 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -372,6 +372,12 @@ (define_c_enum "unspec" > UNSPEC_REPLACE_UN > UNSPEC_VDIVES > UNSPEC_VDIVEU > + UNSPEC_XXEVAL > + UNSPEC_XXSPLTIW > + UNSPEC_XXSPLTID > + UNSPEC_XXSPLTI32DX > + UNSPEC_XXBLEND > + UNSPEC_XXPERMX > ]) > > (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 > @@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2") > (define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12") > (V2DI "8") (V2DF "8")]) > > +;; Like VM2 in altivec.md, just do char, short, int, long, float and double > +(define_mode_iterator VM3 [V4SI > + V8HI > + V16QI > + V4SF > + V2DF > + V2DI]) > + > +(define_mode_attr VM3_char [(V2DI "d") > + (V4SI "w") > + (V8HI "h") > + (V16QI "b") > + (V2DF "d") > + (V4SF "w")]) > + > + > ;; VSX moves > > ;; The patterns for LE permuted loads and stores come before the general > @@ -6383,3 +6405,187 @@ (define_insn "mulv2di3" > "TARGET_POWER10" > "vmulld %0,%1,%2" > [(set_attr "type" "veccomplex")]) > + > + > +;; XXSPLTIW built-in function support > +(define_insn "xxspltiw_v4si" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > + "xxspltiw %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +(define_expand "xxspltiw_v4sf" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > +{ > + long value = rs6000_const_f32_to_i32 (operands[1]); > + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); > + DONE; > +}) > + > +(define_insn "xxspltiw_v4sf_inst" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > + "xxspltiw %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXSPLTIDP built-in function support > +(define_expand "xxspltidp_v2df" > + [(set (match_operand:V2DF 0 "register_operand" ) > + (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] > + UNSPEC_XXSPLTID))] > + "TARGET_POWER10" > +{ > + long value = rs6000_const_f32_to_i32 (operands[1]); > + rs6000_emit_xxspltidp_v2df (operands[0], value); > + DONE; > +}) > + > +(define_insn "xxspltidp_v2df_inst" > + [(set (match_operand:V2DF 0 "register_operand" "=wa") > + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > + UNSPEC_XXSPLTID))] > + "TARGET_POWER10" > + "xxspltidp %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXSPLTI32DX built-in function support > +(define_expand "xxsplti32dx_v4si" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > +{ > + int index = INTVAL (operands[2]); > + > + if (!BYTES_BIG_ENDIAN) > + index = 1 - index; > + > + emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1], > + GEN_INT (index), operands[3])); > + DONE; > +} > + [(set_attr "type" "vecsimple")]) > + > +(define_insn "xxsplti32dx_v4si_inst" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > + "xxsplti32dx %x0,%2,%3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +(define_expand "xxsplti32dx_v4sf" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SF 3 "const_double_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > +{ > + int index = INTVAL (operands[2]); > + long value = rs6000_const_f32_to_i32 (operands[3]); > + if (!BYTES_BIG_ENDIAN) > + index = 1 - index; > + > + emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1], > + GEN_INT (index), GEN_INT (value))); > + DONE; > +}) > + > +(define_insn "xxsplti32dx_v4sf_inst" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > + "xxsplti32dx %x0,%2,%3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXBLEND built-in function support > +(define_insn "xxblend_" > + [(set (match_operand:VM3 0 "register_operand" "=wa") > + (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa") > + (match_operand:VM3 2 "register_operand" "wa") > + (match_operand:VM3 3 "register_operand" "wa")] > + UNSPEC_XXBLEND))] > + "TARGET_POWER10" > + "xxblendv %x0,%x1,%x2,%x3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXPERMX built-in function support > +(define_expand "xxpermx" > + [(set (match_operand:V2DI 0 "register_operand" "+wa") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > + (match_operand:V2DI 2 "register_operand" "wa") > + (match_operand:V16QI 3 "register_operand" "wa") > + (match_operand:QI 4 "u8bit_cint_operand" "n")] > + UNSPEC_XXPERMX))] > + "TARGET_POWER10" > +{ > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_xxpermx_inst (operands[0], operands[1], > + operands[2], operands[3], > + operands[4])); > + else > + { > + /* Reverse value of byte element indexes by XORing with 0xFF. > + Reverse the 32-byte section identifier match by subracting bits [0:2] > + of elemet from 7. */ > + int value = INTVAL (operands[4]); > + rtx vreg = gen_reg_rtx (V16QImode); > + > + emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); > + emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); > + value = 7 - value; > + emit_insn (gen_xxpermx_inst (operands[0], operands[2], > + operands[1], operands[3], > + GEN_INT (value))); > + } > + > + DONE; > +} > + [(set_attr "type" "vecsimple")]) > + > +(define_insn "xxpermx_inst" > + [(set (match_operand:V2DI 0 "register_operand" "+v") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") > + (match_operand:V2DI 2 "register_operand" "v") > + (match_operand:V16QI 3 "register_operand" "v") > + (match_operand:QI 4 "u3bit_cint_operand" "n")] > + UNSPEC_XXPERMX))] > + "TARGET_POWER10" > + "xxpermx %x0,%x1,%x2,%x3,%4" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXEVAL built-in function support > +(define_insn "xxeval" > + [(set (match_operand:V2DI 0 "register_operand" "=wa") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > + (match_operand:V2DI 2 "register_operand" "wa") > + (match_operand:V2DI 3 "register_operand" "wa") > + (match_operand:QI 4 "u8bit_cint_operand" "n")] > + UNSPEC_XXEVAL))] > + "TARGET_POWER10" > + "xxeval %0,%1,%2,%3,%4" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > -- > 2.31.1 > --- > gcc/config/rs6000/altivec.md | 197 --------------------------------- > gcc/config/rs6000/vsx.md | 206 +++++++++++++++++++++++++++++++++++ > 2 files changed, 206 insertions(+), 197 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index fd86c300981..2c73ddea823 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -175,16 +175,10 @@ (define_c_enum "unspec" > UNSPEC_VPEXTD > UNSPEC_VCLRLB > UNSPEC_VCLRRB > - UNSPEC_XXEVAL > UNSPEC_VSTRIR > UNSPEC_VSTRIL > UNSPEC_SLDB > UNSPEC_SRDB > - UNSPEC_XXSPLTIW > - UNSPEC_XXSPLTID > - UNSPEC_XXSPLTI32DX > - UNSPEC_XXBLEND > - UNSPEC_XXPERMX > ]) > > (define_c_enum "unspecv" > @@ -225,21 +219,6 @@ (define_mode_iterator VM2 [V4SI > (KF "FLOAT128_VECTOR_P (KFmode)") > (TF "FLOAT128_VECTOR_P (TFmode)")]) > > -;; Like VM2, just do char, short, int, long, float and double > -(define_mode_iterator VM3 [V4SI > - V8HI > - V16QI > - V4SF > - V2DF > - V2DI]) > - > -(define_mode_attr VM3_char [(V2DI "d") > - (V4SI "w") > - (V8HI "h") > - (V16QI "b") > - (V2DF "d") > - (V4SF "w")]) > - > ;; Map the Vector convert single precision to double precision for integer > ;; versus floating point > (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")]) > @@ -859,170 +838,6 @@ (define_insn "vsdb_" > "vsdbi %0,%1,%2,%3" > [(set_attr "type" "vecsimple")]) > > -(define_insn "xxspltiw_v4si" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > - "xxspltiw %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxspltiw_v4sf" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > -{ > - long value = rs6000_const_f32_to_i32 (operands[1]); > - emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); > - DONE; > -}) > - > -(define_insn "xxspltiw_v4sf_inst" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > - UNSPEC_XXSPLTIW))] > - "TARGET_POWER10" > - "xxspltiw %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxspltidp_v2df" > - [(set (match_operand:V2DF 0 "register_operand" ) > - (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] > - UNSPEC_XXSPLTID))] > - "TARGET_POWER10" > -{ > - long value = rs6000_const_f32_to_i32 (operands[1]); > - rs6000_emit_xxspltidp_v2df (operands[0], value); > - DONE; > -}) > - > -(define_insn "xxspltidp_v2df_inst" > - [(set (match_operand:V2DF 0 "register_operand" "=wa") > - (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > - UNSPEC_XXSPLTID))] > - "TARGET_POWER10" > - "xxspltidp %x0,%1" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxsplti32dx_v4si" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > -{ > - int index = INTVAL (operands[2]); > - > - if (!BYTES_BIG_ENDIAN) > - index = 1 - index; > - > - emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1], > - GEN_INT (index), operands[3])); > - DONE; > -} > - [(set_attr "type" "vecsimple")]) > - > -(define_insn "xxsplti32dx_v4si_inst" > - [(set (match_operand:V4SI 0 "register_operand" "=wa") > - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > - "xxsplti32dx %x0,%2,%3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxsplti32dx_v4sf" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SF 3 "const_double_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > -{ > - int index = INTVAL (operands[2]); > - long value = rs6000_const_f32_to_i32 (operands[3]); > - if (!BYTES_BIG_ENDIAN) > - index = 1 - index; > - > - emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1], > - GEN_INT (index), GEN_INT (value))); > - DONE; > -}) > - > -(define_insn "xxsplti32dx_v4sf_inst" > - [(set (match_operand:V4SF 0 "register_operand" "=wa") > - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > - (match_operand:QI 2 "u1bit_cint_operand" "n") > - (match_operand:SI 3 "s32bit_cint_operand" "n")] > - UNSPEC_XXSPLTI32DX))] > - "TARGET_POWER10" > - "xxsplti32dx %x0,%2,%3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_insn "xxblend_" > - [(set (match_operand:VM3 0 "register_operand" "=wa") > - (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa") > - (match_operand:VM3 2 "register_operand" "wa") > - (match_operand:VM3 3 "register_operand" "wa")] > - UNSPEC_XXBLEND))] > - "TARGET_POWER10" > - "xxblendv %x0,%x1,%x2,%x3" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > -(define_expand "xxpermx" > - [(set (match_operand:V2DI 0 "register_operand" "+wa") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > - (match_operand:V2DI 2 "register_operand" "wa") > - (match_operand:V16QI 3 "register_operand" "wa") > - (match_operand:QI 4 "u8bit_cint_operand" "n")] > - UNSPEC_XXPERMX))] > - "TARGET_POWER10" > -{ > - if (BYTES_BIG_ENDIAN) > - emit_insn (gen_xxpermx_inst (operands[0], operands[1], > - operands[2], operands[3], > - operands[4])); > - else > - { > - /* Reverse value of byte element indexes by XORing with 0xFF. > - Reverse the 32-byte section identifier match by subracting bits [0:2] > - of elemet from 7. */ > - int value = INTVAL (operands[4]); > - rtx vreg = gen_reg_rtx (V16QImode); > - > - emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); > - emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); > - value = 7 - value; > - emit_insn (gen_xxpermx_inst (operands[0], operands[2], > - operands[1], operands[3], > - GEN_INT (value))); > - } > - > - DONE; > -} > - [(set_attr "type" "vecsimple")]) > - > -(define_insn "xxpermx_inst" > - [(set (match_operand:V2DI 0 "register_operand" "+v") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") > - (match_operand:V2DI 2 "register_operand" "v") > - (match_operand:V16QI 3 "register_operand" "v") > - (match_operand:QI 4 "u3bit_cint_operand" "n")] > - UNSPEC_XXPERMX))] > - "TARGET_POWER10" > - "xxpermx %x0,%x1,%x2,%x3,%4" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > (define_expand "vstrir_" > [(set (match_operand:VIshort 0 "altivec_register_operand") > (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] > @@ -3873,18 +3688,6 @@ (define_insn "vperm_v16qiv8hi" > [(set_attr "type" "vecperm") > (set_attr "isa" "p9v,*")]) > > -(define_insn "xxeval" > - [(set (match_operand:V2DI 0 "register_operand" "=wa") > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > - (match_operand:V2DI 2 "register_operand" "wa") > - (match_operand:V2DI 3 "register_operand" "wa") > - (match_operand:QI 4 "u8bit_cint_operand" "n")] > - UNSPEC_XXEVAL))] > - "TARGET_POWER10" > - "xxeval %0,%1,%2,%3,%4" > - [(set_attr "type" "vecsimple") > - (set_attr "prefixed" "yes")]) > - > (define_expand "vec_unpacku_hi_v16qi" > [(set (match_operand:V8HI 0 "register_operand" "=v") > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 441735df9c3..e4ca6e94d49 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -372,6 +372,12 @@ (define_c_enum "unspec" > UNSPEC_REPLACE_UN > UNSPEC_VDIVES > UNSPEC_VDIVEU > + UNSPEC_XXEVAL > + UNSPEC_XXSPLTIW > + UNSPEC_XXSPLTID > + UNSPEC_XXSPLTI32DX > + UNSPEC_XXBLEND > + UNSPEC_XXPERMX > ]) > > (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 > @@ -392,6 +398,22 @@ (define_mode_attr REPLACE_ELT_sh [(V4SI "2") (V4SF "2") > (define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12") > (V2DI "8") (V2DF "8")]) > > +;; Like VM2 in altivec.md, just do char, short, int, long, float and double > +(define_mode_iterator VM3 [V4SI > + V8HI > + V16QI > + V4SF > + V2DF > + V2DI]) > + > +(define_mode_attr VM3_char [(V2DI "d") > + (V4SI "w") > + (V8HI "h") > + (V16QI "b") > + (V2DF "d") > + (V4SF "w")]) > + > + > ;; VSX moves > > ;; The patterns for LE permuted loads and stores come before the general > @@ -6383,3 +6405,187 @@ (define_insn "mulv2di3" > "TARGET_POWER10" > "vmulld %0,%1,%2" > [(set_attr "type" "veccomplex")]) > + > + > +;; XXSPLTIW built-in function support > +(define_insn "xxspltiw_v4si" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > + "xxspltiw %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +(define_expand "xxspltiw_v4sf" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > +{ > + long value = rs6000_const_f32_to_i32 (operands[1]); > + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); > + DONE; > +}) > + > +(define_insn "xxspltiw_v4sf_inst" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > + UNSPEC_XXSPLTIW))] > + "TARGET_POWER10" > + "xxspltiw %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXSPLTIDP built-in function support > +(define_expand "xxspltidp_v2df" > + [(set (match_operand:V2DF 0 "register_operand" ) > + (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] > + UNSPEC_XXSPLTID))] > + "TARGET_POWER10" > +{ > + long value = rs6000_const_f32_to_i32 (operands[1]); > + rs6000_emit_xxspltidp_v2df (operands[0], value); > + DONE; > +}) > + > +(define_insn "xxspltidp_v2df_inst" > + [(set (match_operand:V2DF 0 "register_operand" "=wa") > + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] > + UNSPEC_XXSPLTID))] > + "TARGET_POWER10" > + "xxspltidp %x0,%1" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXSPLTI32DX built-in function support > +(define_expand "xxsplti32dx_v4si" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > +{ > + int index = INTVAL (operands[2]); > + > + if (!BYTES_BIG_ENDIAN) > + index = 1 - index; > + > + emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1], > + GEN_INT (index), operands[3])); > + DONE; > +} > + [(set_attr "type" "vecsimple")]) > + > +(define_insn "xxsplti32dx_v4si_inst" > + [(set (match_operand:V4SI 0 "register_operand" "=wa") > + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > + "xxsplti32dx %x0,%2,%3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +(define_expand "xxsplti32dx_v4sf" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SF 3 "const_double_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > +{ > + int index = INTVAL (operands[2]); > + long value = rs6000_const_f32_to_i32 (operands[3]); > + if (!BYTES_BIG_ENDIAN) > + index = 1 - index; > + > + emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1], > + GEN_INT (index), GEN_INT (value))); > + DONE; > +}) > + > +(define_insn "xxsplti32dx_v4sf_inst" > + [(set (match_operand:V4SF 0 "register_operand" "=wa") > + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") > + (match_operand:QI 2 "u1bit_cint_operand" "n") > + (match_operand:SI 3 "s32bit_cint_operand" "n")] > + UNSPEC_XXSPLTI32DX))] > + "TARGET_POWER10" > + "xxsplti32dx %x0,%2,%3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXBLEND built-in function support > +(define_insn "xxblend_" > + [(set (match_operand:VM3 0 "register_operand" "=wa") > + (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa") > + (match_operand:VM3 2 "register_operand" "wa") > + (match_operand:VM3 3 "register_operand" "wa")] > + UNSPEC_XXBLEND))] > + "TARGET_POWER10" > + "xxblendv %x0,%x1,%x2,%x3" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXPERMX built-in function support > +(define_expand "xxpermx" > + [(set (match_operand:V2DI 0 "register_operand" "+wa") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > + (match_operand:V2DI 2 "register_operand" "wa") > + (match_operand:V16QI 3 "register_operand" "wa") > + (match_operand:QI 4 "u8bit_cint_operand" "n")] > + UNSPEC_XXPERMX))] > + "TARGET_POWER10" > +{ > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_xxpermx_inst (operands[0], operands[1], > + operands[2], operands[3], > + operands[4])); > + else > + { > + /* Reverse value of byte element indexes by XORing with 0xFF. > + Reverse the 32-byte section identifier match by subracting bits [0:2] > + of elemet from 7. */ > + int value = INTVAL (operands[4]); > + rtx vreg = gen_reg_rtx (V16QImode); > + > + emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); > + emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); > + value = 7 - value; > + emit_insn (gen_xxpermx_inst (operands[0], operands[2], > + operands[1], operands[3], > + GEN_INT (value))); > + } > + > + DONE; > +} > + [(set_attr "type" "vecsimple")]) > + > +(define_insn "xxpermx_inst" > + [(set (match_operand:V2DI 0 "register_operand" "+v") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") > + (match_operand:V2DI 2 "register_operand" "v") > + (match_operand:V16QI 3 "register_operand" "v") > + (match_operand:QI 4 "u3bit_cint_operand" "n")] > + UNSPEC_XXPERMX))] > + "TARGET_POWER10" > + "xxpermx %x0,%x1,%x2,%x3,%4" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > + > +;; XXEVAL built-in function support > +(define_insn "xxeval" > + [(set (match_operand:V2DI 0 "register_operand" "=wa") > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") > + (match_operand:V2DI 2 "register_operand" "wa") > + (match_operand:V2DI 3 "register_operand" "wa") > + (match_operand:QI 4 "u8bit_cint_operand" "n")] > + UNSPEC_XXEVAL))] > + "TARGET_POWER10" > + "xxeval %0,%1,%2,%3,%4" > + [(set_attr "type" "vecsimple") > + (set_attr "prefixed" "yes")]) > +