From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id C64D63858CDB for ; Mon, 26 Feb 2024 15:59:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C64D63858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C64D63858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708963143; cv=none; b=Z1a4F2d11vWmlwYhSPEkGjwOWHETDHbxPk7KVuVMk+35EqMZCUfzW86dZJNM8PkIxxNGWAPKMTocvyLmwf9yb/PdnEJ2KEM3H9QoIReKoffvjbLrSRaWHfmY2EUTU4ZcfvDy37IUfSsnPceHarFeBh90AnT2rG7fs1TFaSrA2f0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708963143; c=relaxed/simple; bh=GnKBEUyQesdeh4azE22C9fRc0s9d5nnmMeWzPxkwTRs=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=rEsLH3up18nxIQompEZYR1YvSDOI6pBz8l26HnBQXNft/bP+bF3mqWrgQSq5gJx1WUtmzf9BFXBO8HdFgZ0/FqC3b07DTrpvouOOTykXflKzCdHXqaWCduA/aVLxiQtaxm2tJ2Goo4aoj+aV9kjsZGTLbOQL7AJj1S5NoFtrf4M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2604DA7; Mon, 26 Feb 2024 07:59:38 -0800 (PST) Received: from [10.2.78.54] (e120077-lin.cambridge.arm.com [10.2.78.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C791D3F73F; Mon, 26 Feb 2024 07:58:59 -0800 (PST) Message-ID: Date: Mon, 26 Feb 2024 15:58:58 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ARM: Fix conditional execution [PR113915] Content-Language: en-GB To: Wilco Dijkstra , Kyrylo Tkachov Cc: GCC Patches References: From: "Richard Earnshaw (lists)" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3497.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 23/02/2024 15:46, Wilco Dijkstra wrote: > Hi Richard, > >> This bit isn't.  The correct fix here is to fix the pattern(s) concerned to add the missing predicate. >> >> Note that builtin-bswap.x explicitly mentions predicated mnemonics in the comments. > > I fixed the patterns in v2. There are likely some more, plus we could likely merge many t1 and t2 > patterns where the only difference is predication. But those cleanups are for another time... > > Cheers, > Wilco > > v2: Add predicable to the rev patterns. > > By default most patterns can be conditionalized on Arm targets. However > Thumb-2 predication requires the "predicable" attribute be explicitly > set to "yes". Most patterns are shared between Arm and Thumb(-2) and are > marked with "predicable". Given this sharing, it does not make sense to > use a different default for Arm. So only consider conditional execution > of instructions that have the predicable attribute set to yes. This ensures > that patterns not explicitly marked as such are never conditionally executed. > > Passes regress and bootstrap, OK for commit? > > gcc/ChangeLog: > PR target/113915 > * config/arm/arm.md (NOCOND): Improve comment. > (arm_rev*) Add predicable. > * config/arm/arm.cc (arm_final_prescan_insn): Add check for > PREDICABLE_YES. > > gcc/testsuite/ChangeLog: > PR target/113915 > * gcc.target/arm/builtin-bswap-1.c: Fix test. > > --- > > diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc > index 1cd69268ee986a0953cc85ab259355d2191250ac..6a35fe44138135998877a9fb74c2a82a7f99dcd5 100644 > --- a/gcc/config/arm/arm.cc > +++ b/gcc/config/arm/arm.cc > @@ -25613,11 +25613,12 @@ arm_final_prescan_insn (rtx_insn *insn) > break; > > case INSN: > - /* Instructions using or affecting the condition codes make it > - fail. */ > + /* Check the instruction is explicitly marked as predicable. > + Instructions using or affecting the condition codes are not. */ > scanbody = PATTERN (this_insn); > if (!(GET_CODE (scanbody) == SET > || GET_CODE (scanbody) == PARALLEL) > + || get_attr_predicable (this_insn) != PREDICABLE_YES > || get_attr_conds (this_insn) != CONDS_NOCOND) > fail = TRUE; > break; > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 5816409f86f1106b410c5e21d77e599b485f85f2..81237a61d4a2ebcfb77e47c2bd29137aba28a521 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -307,6 +307,8 @@ > ; > ; NOCOND means that the instruction does not use or alter the condition > ; codes but can be converted into a conditionally exectuted instruction. > +; Given that NOCOND is the default for most instructions if omitted, > +; the attribute predicable must be set to yes as well. > > (define_attr "conds" "use,set,clob,unconditional,nocond" > (if_then_else > @@ -12547,6 +12549,7 @@ > revsh%?\t%0, %1" > [(set_attr "arch" "t1,t2,32") > (set_attr "length" "2,2,4") > + (set_attr "predicable" "no,yes,yes") > (set_attr "type" "rev")] > ) > > @@ -12560,6 +12563,7 @@ > rev16%?\t%0, %1" > [(set_attr "arch" "t1,t2,32") > (set_attr "length" "2,2,4") > + (set_attr "predicable" "no,yes,yes") > (set_attr "type" "rev")] > ) > > @@ -12584,6 +12588,7 @@ > rev16%?\t%0, %1" > [(set_attr "arch" "t1,t2,32") > (set_attr "length" "2,2,4") > + (set_attr "predicable" "no,yes,yes") > (set_attr "type" "rev")] > ) > > @@ -12619,6 +12624,7 @@ > rev16%?\t%0, %1" > [(set_attr "arch" "t1,t2,32") > (set_attr "length" "2,2,4") > + (set_attr "predicable" "no,yes,yes") > (set_attr "type" "rev")] > ) > > diff --git a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c > index c1e7740d14d3ca4e93a71e38b12f82c19791a204..1a311a6a5af647d40abd553e5d0ba1273c76d288 100644 > --- a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c > +++ b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c > @@ -5,14 +5,11 @@ > of the instructions. Add an -mtune option known to facilitate that. */ > /* { dg-additional-options "-O2 -mtune=cortex-a53" } */ > /* { dg-final { scan-assembler-not "orr\[ \t\]" } } */ > -/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb } } } } */ > -/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb } } } } */ > +/* { dg-final { scan-assembler-times "revsh\\t" 1 } } */ > +/* { dg-final { scan-assembler-times "revshne\\t" 1 } } */ > +/* { dg-final { scan-assembler-times "rev16\\t" 1 } } */ > +/* { dg-final { scan-assembler-times "rev16ne\\t" 1 } } */ > +/* { dg-final { scan-assembler-times "rev\\t" 2 } } */ > +/* { dg-final { scan-assembler-times "revne\\t" 2 } } */ > > #include "builtin-bswap.x" > Did you test this on a thumb1 target? It seems to me that the target parts that you've removed were likely related to that. In fact, I don't see why this test would need to be changed at all. R.