From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id BA49E3858416 for ; Wed, 31 Jul 2024 08:57:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BA49E3858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BA49E3858416 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722416257; cv=none; b=Qi2cI4lxQ0lFgvYAQaGassuiUGqkahibbciOTGu6GeeSP+cL5nKdnLRXWEGLWlNN4CogQ5LBL9fRodnSk2djGrvs9z1N3aEwW6X+Uld8KZ15r0k2Qgx+hl86asYbvBk7IRjcCUq0+gWZCW7bwZ9mmnIlib160phlQ9A1Lk3mxZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722416257; c=relaxed/simple; bh=DATaaoEo7sm/CT8x8dsZowgd5YDMseE1dHsgrOf/FKY=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=DmHVfjvEusdAMMVTrLvGW1y95PLLLfYLNsaz2T7D/aB2m8w7u/12UbpFtBC/WttoDvbpoJYBZh0ioGRRfdaJijR63kBYPURP1qSimZ4W3rb4fcmLcvPgmSVTtIdFBbvkUtiImuitVqBGSXpe3jIT8W6xUL4Cc5T0ue+0NcpDzI0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8CxvOp5_KlmoAMFAA--.17515S3; Wed, 31 Jul 2024 16:57:29 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by front1 (Coremail) with SMTP id qMiowMAxysV2_Klmlg8IAA--.39896S3; Wed, 31 Jul 2024 16:57:27 +0800 (CST) Subject: Re: [PATCH] LoongArch: Rework bswap{hi,si,di}2 definition To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn References: <20240729075837.6060-1-xry111@xry111.site> From: Lulu Cheng Message-ID: Date: Wed, 31 Jul 2024 16:57:26 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20240729075837.6060-1-xry111@xry111.site> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:qMiowMAxysV2_Klmlg8IAA--.39896S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxtFy8tFyUKr4xWF4UCF18tFc_yoWxAFW3p3 9rC3WktFW8Zrs7K34I9ayjqrnxGr1xGF4j9FZxXr9FkryUW34qgw1vkrZIqFyUGwnYvF4j qa1rX348WF45KwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUv2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07 AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1CP fJUUUUU== X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: ÔÚ 2024/7/29 ÏÂÎç3:58, Xi Ruoyao дµÀ: > Per a gcc-help thread we are generating sub-optimal code for > __builtin_bswap{32,64}. To fix it: > > - Use a single revb.d instruction for bswapdi2. > - Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT, > revb.2h + rotri.w for !TARGET_64BIT. > - Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single > revb.2w instruction for bswapdi2 (x) r>> 32. > > Unfortunately I cannot figure out a way to make the compiler generate > revb.4h or revh.{2w,d} instructions. This optimization is really ingenious and I have no problem. I also haven't figured out how to generate revb.4h or revh. {2w,d}. I think we can merge this patch first. Thanks. > > gcc/ChangeLog: > > * config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H, > UNSPEC_REVH_D): Remove UNSPECs. > (revb_4h, revh_d): Remove define_insn. > (revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of > an UNSPEC. > (revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn. > (bswapsi2): Change to define_expand. Only expand to revb.2h + > rotri.w if !TARGET_64BIT. > (bswapdi2): Change to define_insn of which the output is just a > revb.d instruction. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/revb.c: New test. > --- > > Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? > > gcc/config/loongarch/loongarch.md | 79 ++++++++++++----------- > gcc/testsuite/gcc.target/loongarch/revb.c | 61 +++++++++++++++++ > 2 files changed, 104 insertions(+), 36 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/loongarch/revb.c > > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index ac94a22eafc..f166e834c56 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -20,11 +20,6 @@ > ;; . > > (define_c_enum "unspec" [ > - ;; Integer operations that are too cumbersome to describe directly. > - UNSPEC_REVB_2H > - UNSPEC_REVB_4H > - UNSPEC_REVH_D > - > ;; Floating-point moves. > UNSPEC_LOAD_LOW > UNSPEC_LOAD_HIGH > @@ -3155,55 +3150,67 @@ (define_insn "alslsi3_extend" > > ;; Reverse the order of bytes of operand 1 and store the result in operand 0. > > -(define_insn "bswaphi2" > - [(set (match_operand:HI 0 "register_operand" "=r") > - (bswap:HI (match_operand:HI 1 "register_operand" "r")))] > +(define_insn "revb_2h" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (rotatert:SI (bswap:SI (match_operand:SI 1 "register_operand" "r")) > + (const_int 16)))] > "" > "revb.2h\t%0,%1" > [(set_attr "type" "shift")]) > > -(define_insn_and_split "bswapsi2" > - [(set (match_operand:SI 0 "register_operand" "=r") > - (bswap:SI (match_operand:SI 1 "register_operand" "r")))] > - "" > - "#" > - "" > - [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_REVB_2H)) > - (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] > - "" > - [(set_attr "insn_count" "2")]) > - > -(define_insn_and_split "bswapdi2" > +(define_insn "revb_2h_extend" > [(set (match_operand:DI 0 "register_operand" "=r") > - (bswap:DI (match_operand:DI 1 "register_operand" "r")))] > + (sign_extend:DI > + (rotatert:SI > + (bswap:SI (match_operand:SI 1 "register_operand" "r")) > + (const_int 16))))] > "TARGET_64BIT" > - "#" > - "" > - [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_REVB_4H)) > - (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_REVH_D))] > - "" > - [(set_attr "insn_count" "2")]) > + "revb.2h\t%0,%1" > + [(set_attr "type" "shift")]) > > -(define_insn "revb_2h" > - [(set (match_operand:SI 0 "register_operand" "=r") > - (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_REVB_2H))] > +(define_insn "bswaphi2" > + [(set (match_operand:HI 0 "register_operand" "=r") > + (bswap:HI (match_operand:HI 1 "register_operand" "r")))] > "" > "revb.2h\t%0,%1" > [(set_attr "type" "shift")]) > > -(define_insn "revb_4h" > +(define_insn "revb_2w" > [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVB_4H))] > + (rotatert:DI (bswap:DI (match_operand:DI 1 "register_operand" "r")) > + (const_int 32)))] > "TARGET_64BIT" > - "revb.4h\t%0,%1" > + "revb.2w\t%0,%1" > [(set_attr "type" "shift")]) > > -(define_insn "revh_d" > +(define_insn "*bswapsi2" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] > + "TARGET_64BIT" > + "revb.2w\t%0,%1" > + [(set_attr "type" "shift")]) > + > +(define_expand "bswapsi2" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] > + "" > +{ > + if (!TARGET_64BIT) > + { > + rtx t = gen_reg_rtx (SImode); > + emit_insn (gen_revb_2h (t, operands[1])); > + emit_insn (gen_rotrsi3 (operands[0], t, GEN_INT (16))); > + DONE; > + } > +}) > + > +(define_insn "bswapdi2" > [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVH_D))] > + (bswap:DI (match_operand:DI 1 "register_operand" "r")))] > "TARGET_64BIT" > - "revh.d\t%0,%1" > + "revb.d\t%0,%1" > [(set_attr "type" "shift")]) > + > > ;; > ;; .................... > diff --git a/gcc/testsuite/gcc.target/loongarch/revb.c b/gcc/testsuite/gcc.target/loongarch/revb.c > new file mode 100644 > index 00000000000..27a5d0fc7b7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/revb.c > @@ -0,0 +1,61 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +/* > +**t1: > +** revb.2w \$r4,\$r4 > +** slli.w \$r4,\$r4,0 > +** jr \$r1 > +*/ > +unsigned int > +t1 (unsigned int x) > +{ > + return __builtin_bswap32 (x); > +} > + > +/* > +**t2: > +** revb.d \$r4,\$r4 > +** jr \$r1 > +*/ > +unsigned long > +t2 (unsigned long x) > +{ > + return __builtin_bswap64 (x); > +} > + > +/* > +**t3: > +** revb.2h \$r4,\$r4 > +** jr \$r1 > +*/ > +unsigned int > +t3 (unsigned int x) > +{ > + return (x >> 8) & 0xff00ff | (x << 8) & 0xff00ff00; > +} > + > +/* > +**t4: > +** revb.2w \$r4,\$r4 > +** jr \$r1 > +*/ > +unsigned long > +t4 (unsigned long x) > +{ > + x = __builtin_bswap64 (x); > + return x << 32 | x >> 32; > +} > + > +/* > +**t5: > +** revb.2h \$r4,\$r4 > +** bstrpick.w \$r4,\$r4,15,0 > +** jr \$r1 > +*/ > +unsigned short > +t5 (unsigned short x) > +{ > + return __builtin_bswap16 (x); > +}