From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 30A403858D20 for ; Tue, 2 Apr 2024 06:25:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 30A403858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 30A403858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712039157; cv=none; b=EvdX09QV9QP1xY2VwnKEDDRF3/2RcvLiUuF3hEeZbxPSxG75FsowqIfd3i8gjo2cHMlgb9vcpIOx5p8tl0FsdQlsUpDNqrSutjnxRQr/M99ElUcuXYpWfUJNabvKwdnSwyli8axMn1RlOx9mZ2ZOIWA27qH8hsBNN1iWi9rCop0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712039157; c=relaxed/simple; bh=J7V8G8GcRN7/NovhZX9ZByNwtkes5fMs1384akxsvzc=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=QC5JNVB4yPkdpOho+oqs6xBeweEMy5rAPD6HeZDdfuwXBLkzKiKrYH+T+v31M7rFvqPSFuH8slG4qma8nnnbrjWMAnbWuRw9QOGvwVGAAFYE7/Hs1W8SrbQyzWNmTyijKGUHKX8tjTOvmW8QH1FIE/aV91huv5QwMLFxHdxV/a8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [154.8.197.246]) by gateway (Coremail) with SMTP id _____8DxWPDspAtmpTkiAA--.12729S3; Tue, 02 Apr 2024 14:25:48 +0800 (CST) Received: from [10.0.8.10] (unknown [154.8.197.246]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxzM7opAtmnI1xAA--.16298S2; Tue, 02 Apr 2024 14:25:44 +0800 (CST) Content-Type: multipart/alternative; boundary="------------5960gkOJ6Yop29ovsD8FgrGf" Message-ID: Date: Tue, 2 Apr 2024 14:25:44 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] LoongArch: Remove unused code and add sign/zero-extend for vpickve2gr.d To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn References: <20240322080354.28356-1-xujiahao@loongson.cn> From: xujiahao In-Reply-To: <20240322080354.28356-1-xujiahao@loongson.cn> X-CM-TRANSID:AQAAf8DxzM7opAtmnI1xAA--.16298S2 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoW3KFWxKr47XFW8Zw1UGFy7twc_yoWDZFyUpr Zrua47Ar48JFn0g34ktay5Xws0kryxKa12vF9xJ397Cry5Ww1qqa40kr9IqFyYvw4Sg3y3 Xa10qa15uan8KwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3fc02F40Ex7xS67I2xxkvbII20VAFz48EcVAYj2Uv73VFW2AGmfu7bjvj m3AaLaJ3UjIYCTnIWjp_UUUY-7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42 xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUGVWUXwA2ocxC64kIII0Yj41l84x0c7CE w4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6x kF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8V C2zVCFFI0UMc02F40Ex7xS67I2xxkvbII20VAFz48EcVAYj21lYx0E2Ix0cI8IcVAFwI0_ Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwI xGrwCjr7xvwVCIw2I0I7xG6c02F41l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUGVWUWwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAI cVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVj vjDU0xZFpf9x07UEFAJUUUUU= X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,HTML_MESSAGE,KAM_DMARC_STATUS,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------5960gkOJ6Yop29ovsD8FgrGf Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit We recently discovered an issue with the sign/zero extension behavior of |[x]vpickve2gr.|The QI , HI and SI are extended to SI instead of DI, which may lead to the generation of additional sign extension instructions. We have decided to fix this issue in the next version. I will upload a new patch later that will only remove unused code. 在 2024/3/22 16:03, Jiahao Xu 写道: > For machines that satisfy ISA_HAS_LSX && !TARGET_64BIT, we will not support them now > and in the future, so this patch removes these unused code. > > This patch also adds sign/zero-extend operations to vpickve2gr.d to match the actual > instruction behavior, and integrates the template definition of vpickve2gr. > > gcc/ChangeLog: > > * config/loongarch/lasx.md: Remove unused code. > * config/loongarch/loongarch-protos.h (loongarch_split_lsx_copy_d): Remove. > (loongarch_split_lsx_insert_d): Ditto. > (loongarch_split_lsx_fill_d): Ditto. > * config/loongarch/loongarch.cc (loongarch_split_lsx_copy_d): Ditto. > (loongarch_split_lsx_insert_d): Ditto. > (loongarch_split_lsx_fill_d): Ditto. > * config/loongarch/lsx.md (lsx_vpickve2gr_): Redefine. > (lsx_vpickve2gr_du): Remove. > (lsx_vpickve2gr_): Ditto. > > diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md > index 2fa5e46c8e8..7bd61f8ed5b 100644 > --- a/gcc/config/loongarch/lasx.md > +++ b/gcc/config/loongarch/lasx.md > @@ -572,12 +572,7 @@ (define_insn "lasx_xvinsgr2vr_" > (match_operand 3 "const__operand" "")))] > "ISA_HAS_LASX" > { > -#if 0 > - if (!TARGET_64BIT && (mode == V4DImode || mode == V4DFmode)) > - return "#"; > - else > -#endif > - return "xvinsgr2vr.\t%u0,%z1,%y3"; > + return "xvinsgr2vr.\t%u0,%z1,%y3"; > } > [(set_attr "type" "simd_insert") > (set_attr "mode" "")]) > @@ -1446,10 +1441,7 @@ (define_insn "lasx_xvreplgr2vr_" > if (which_alternative == 1) > return "xvldi.b\t%u0,0" ; > > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "xvreplgr2vr.\t%u0,%z1"; > + return "xvreplgr2vr.\t%u0,%z1"; > } > [(set_attr "type" "simd_fill") > (set_attr "mode" "") > diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h > index e3ed2b912a5..e238d795a73 100644 > --- a/gcc/config/loongarch/loongarch-protos.h > +++ b/gcc/config/loongarch/loongarch-protos.h > @@ -89,9 +89,6 @@ extern void loongarch_split_128bit_move (rtx, rtx); > extern bool loongarch_split_128bit_move_p (rtx, rtx); > extern void loongarch_split_256bit_move (rtx, rtx); > extern bool loongarch_split_256bit_move_p (rtx, rtx); > -extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx (*)(rtx, rtx, rtx)); > -extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx); > -extern void loongarch_split_lsx_fill_d (rtx, rtx); > extern const char *loongarch_output_move (rtx, rtx); > #ifdef RTX_CODE > extern void loongarch_expand_scc (rtx *); > diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc > index 030957db4e7..34850a0fc64 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -4759,82 +4759,6 @@ loongarch_split_256bit_move (rtx dest, rtx src) > } > } > > - > -/* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function > - used to generate subregs. */ > - > -void > -loongarch_split_lsx_copy_d (rtx dest, rtx src, rtx index, > - rtx (*gen_fn)(rtx, rtx, rtx)) > -{ > - gcc_assert ((GET_MODE (src) == V2DImode && GET_MODE (dest) == DImode) > - || (GET_MODE (src) == V2DFmode && GET_MODE (dest) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low = loongarch_subword (dest, false); > - rtx high = loongarch_subword (dest, true); > - rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0); > - > - emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2))); > - emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1))); > -} > - > -/* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */ > - > -void > -loongarch_split_lsx_insert_d (rtx dest, rtx src1, rtx index, rtx src2) > -{ > - int i; > - gcc_assert (GET_MODE (dest) == GET_MODE (src1)); > - gcc_assert ((GET_MODE (dest) == V2DImode > - && (GET_MODE (src2) == DImode || src2 == const0_rtx)) > - || (GET_MODE (dest) == V2DFmode && GET_MODE (src2) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low = loongarch_subword (src2, false); > - rtx high = loongarch_subword (src2, true); > - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); > - rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0); > - i = exact_log2 (INTVAL (index)); > - gcc_assert (i != -1); > - > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, low, new_src1, > - GEN_INT (1 << (i * 2)))); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, > - GEN_INT (1 << (i * 2 + 1)))); > -} > - > -/* Split FILL.D. */ > - > -void > -loongarch_split_lsx_fill_d (rtx dest, rtx src) > -{ > - gcc_assert ((GET_MODE (dest) == V2DImode > - && (GET_MODE (src) == DImode || src == const0_rtx)) > - || (GET_MODE (dest) == V2DFmode && GET_MODE (src) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low, high; > - if (src == const0_rtx) > - { > - low = src; > - high = src; > - } > - else > - { > - low = loongarch_subword (src, false); > - high = loongarch_subword (src, true); > - } > - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); > - emit_insn (gen_lsx_vreplgr2vr_w (new_dest, low)); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 1))); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 3))); > -} > - > - > /* Return the appropriate instructions to move SRC into DEST. Assume > that SRC is operand 1 and DEST is operand 0. */ > > diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md > index 87d3e7c5d9f..01778a3bd02 100644 > --- a/gcc/config/loongarch/lsx.md > +++ b/gcc/config/loongarch/lsx.md > @@ -582,28 +582,11 @@ (define_insn "lsx_vinsgr2vr_" > (match_operand 3 "const__operand" "")))] > "ISA_HAS_LSX" > { > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "vinsgr2vr.\t%w0,%z1,%y3"; > + return "vinsgr2vr.\t%w0,%z1,%y3"; > } > [(set_attr "type" "simd_insert") > (set_attr "mode" "")]) > > -(define_split > - [(set (match_operand:LSX_D 0 "register_operand") > - (vec_merge:LSX_D > - (vec_duplicate:LSX_D > - (match_operand: 1 "_operand")) > - (match_operand:LSX_D 2 "register_operand") > - (match_operand 3 "const__operand")))] > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_insert_d (operands[0], operands[2], operands[3], operands[1]); > - DONE; > -}) > - > (define_insn "lsx_vextrins__internal" > [(set (match_operand:LSX 0 "register_operand" "=f") > (vec_merge:LSX > @@ -635,69 +618,13 @@ (define_insn "lsx_vpickve2gr_" > [(set (match_operand: 0 "register_operand" "=r") > (any_extend: > (vec_select: > - (match_operand:ILSX_HB 1 "register_operand" "f") > + (match_operand:ILSX 1 "register_operand" "f") > (parallel [(match_operand 2 "const__operand" "")]))))] > "ISA_HAS_LSX" > "vpickve2gr.\t%0,%w1,%2" > [(set_attr "type" "simd_copy") > (set_attr "mode" "")]) > > -(define_insn "lsx_vpickve2gr_" > - [(set (match_operand: 0 "register_operand" "=r") > - (any_extend: > - (vec_select: > - (match_operand:LSX_W 1 "register_operand" "f") > - (parallel [(match_operand 2 "const__operand" "")]))))] > - "ISA_HAS_LSX" > - "vpickve2gr.\t%0,%w1,%2" > - [(set_attr "type" "simd_copy") > - (set_attr "mode" "")]) > - > -(define_insn_and_split "lsx_vpickve2gr_du" > - [(set (match_operand:DI 0 "register_operand" "=r") > - (vec_select:DI > - (match_operand:V2DI 1 "register_operand" "f") > - (parallel [(match_operand 2 "const_0_or_1_operand" "")])))] > - "ISA_HAS_LSX" > -{ > - if (TARGET_64BIT) > - return "vpickve2gr.du\t%0,%w1,%2"; > - else > - return "#"; > -} > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2], > - gen_lsx_vpickve2gr_wu); > - DONE; > -} > - [(set_attr "type" "simd_copy") > - (set_attr "mode" "V2DI")]) > - > -(define_insn_and_split "lsx_vpickve2gr_" > - [(set (match_operand: 0 "register_operand" "=r") > - (vec_select: > - (match_operand:LSX_D 1 "register_operand" "f") > - (parallel [(match_operand 2 "const__operand" "")])))] > - "ISA_HAS_LSX" > -{ > - if (TARGET_64BIT) > - return "vpickve2gr.\t%0,%w1,%2"; > - else > - return "#"; > -} > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2], > - gen_lsx_vpickve2gr_w); > - DONE; > -} > - [(set_attr "type" "simd_copy") > - (set_attr "mode" "")]) > - > - > (define_expand "abs2" > [(match_operand:ILSX 0 "register_operand" "=f") > (abs:ILSX (match_operand:ILSX 1 "register_operand" "f"))] > @@ -1369,25 +1296,11 @@ (define_insn "lsx_vreplgr2vr_" > if (which_alternative == 1) > return "vldi.\t%w0,0"; > > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "vreplgr2vr.\t%w0,%z1"; > + return "vreplgr2vr.\t%w0,%z1"; > } > [(set_attr "type" "simd_fill") > (set_attr "mode" "")]) > > -(define_split > - [(set (match_operand:LSX_D 0 "register_operand") > - (vec_duplicate:LSX_D > - (match_operand: 1 "register_operand")))] > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_fill_d (operands[0], operands[1]); > - DONE; > -}) > - > (define_insn "logb2" > [(set (match_operand:FLSX 0 "register_operand" "=f") > (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] --------------5960gkOJ6Yop29ovsD8FgrGf--