From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 85769385661B for ; Sat, 10 Jun 2023 17:53:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 85769385661B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6532671ccc7so3158108b3a.2 for ; Sat, 10 Jun 2023 10:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686419582; x=1689011582; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=Ft+4qsy5Ud2/S0M0y/HgtoXqnk4pDPmmWAbMUNNv1TI=; b=PewPkCMJw03uEZwcvZoO+R6OJsvT6zVYqWTGJNjI1O4izU+NrHf0h9ywWTHgEloU3T WYk+7RW+Z314ymsUkibN7kY5Fxokhm/LMckLvtxa1hOrU8vr0upJcumRjpbKzerZwqr/ xzcTd7bNhyWxeupbK7zz5hDOOUWA1Jzx9FSWBTNG0DSUyaaOM9aKP/bcCdvK/Dw99LN3 aeoTwv6RVCShLCqRJCvkhHB2DtM9D9NeX+ASmChP/guzaKVqx1Bdn4KnSTKfs/KxtwR3 emEVo+JqRZwlIRA/dAfoMqO66C9bfRIPDFcqGpOmP0/xNNasOStH2ahWAcWJcIoe9pg3 syRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686419582; x=1689011582; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Ft+4qsy5Ud2/S0M0y/HgtoXqnk4pDPmmWAbMUNNv1TI=; b=lqRyK/CQb0014SufI7oVh5Q9cBDumdlIRUxIMkrYtM3XWLv7suLeDframIzy5Q7FdF kQRZ/tU+56igKGiQKWZFdnZb0q1w14Bk0ueWv39ucFEdM5wx8Ejoe4+70YOM2jQxVV4d vqqwuEI6Tr5Mlv4xop6JCSoFC1dVCkYj9TniHaGrCm7F4BSf8C1NNN8yxw13qHv5l2Gw P7Ve92ZwlH5MtSbUIGNuqJ4aNafLKyRjy96xOYZbBws/t6838YVNS9aatpTt0LSWVvhE Dh5TBtZ5vgdfu3qA3R7urQjLNiScKsqHVVWEsQm44qM42zpIslY3c/UQpIPA9+MoANwi 8lQw== X-Gm-Message-State: AC+VfDy89qqd9LsvHUeO9QfwfGwSJbs6Uxuk9MkWp+DcNWGTpNm2ISVK P94Xvwh+DwAibaYEfwi5lvs= X-Google-Smtp-Source: ACHHUZ5H9gDTR6BcO+B/uZzmjTuYEKJquFwMuFMCfHmAFQJ0l9mkPj/HsVVfEQPK+S89SfNmcnfEPA== X-Received: by 2002:a05:6a20:549e:b0:119:e18c:ea9 with SMTP id i30-20020a056a20549e00b00119e18c0ea9mr3812460pzk.50.1686419582176; Sat, 10 Jun 2023 10:53:02 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id u22-20020aa78496000000b0064ff643f954sm4387779pfn.88.2023.06.10.10.53.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jun 2023 10:53:01 -0700 (PDT) Message-ID: Date: Sat, 10 Jun 2023 11:53:00 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension Content-Language: en-US To: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230428062314.2995571-1-christoph.muellner@vrull.eu> From: Jeff Law In-Reply-To: <20230428062314.2995571-1-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_MANYTO,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/28/23 00:23, Christoph Muellner wrote: > From: Christoph Müllner > > The XTheadMemIdx ISA extension provides a additional load and store > instructions with new addressing modes. > > The following memory accesses types are supported: > * ltype = [b,bu,h,hu,w,wu,d] > * stype = [b,h,w,d] > > The following addressing modes are supported: > * immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions): > l.ia, l.ib, s.ia, s.ib > * register offset with additional immediate offset (11 instructions): > lr, sr > * zero-extended register offset with additional immediate offset > (11 instructions): lur, sur > > The RISC-V base ISA does not support index registers, so the changes > are kept separate from the RISC-V standard support. > > Similar like other extensions (Zbb, XTheadBb), this patch needs to > prevent the conversion of sign-extensions/zero-extensions into > shift instructions. The case of the zero-extended register offset > addressing mode is handled by a new peephole pass. > > Handling the different cases of extensions results in a couple of INSNs > that look redundant on first view, but they are just the equivalent > of what we already have for Zbb as well. The only difference is, that > we have much more load instructions. > > To fully utilize the capabilities of the instructions, there are > a few new peephole passes which fold shift amounts into the RTX > if possible. The added tests ensure that this feature won't > regress without notice. > > We already have a constraint with the name 'th_f_fmv', therefore, > the new constraints follow this pattern and have the same length > as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu'). > > gcc/ChangeLog: > > * config/riscv/constraints.md (th_m_mia): New constraint. > (th_m_mib): Likewise. > (th_m_mir): Likewise. > (th_m_miu): Likewise. > * config/riscv/riscv-protos.h (enum riscv_address_type): > Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG, > and ADDRESS_REG_WB and their documentation. > (struct riscv_address_info): Add new field 'shift' and > document the field usage for the new address types. > (riscv_valid_base_register_p): New prototype. > (th_memidx_legitimate_modify_p): Likewise. > (th_memidx_legitimate_index_p): Likewise. > (th_classify_address): Likewise. > (th_output_move): Likewise. > (th_print_operand_address): Likewise. > * config/riscv/riscv.cc (riscv_index_reg_class): > Return GR_REGS for XTheadMemIdx. > (riscv_regno_ok_for_index_p): Add support for XTheadMemIdx. > (riscv_classify_address): Call th_classify_address() on top. > (riscv_output_move): Call th_output_move() on top. > (riscv_print_operand_address): Call th_print_operand_address() > on top. > * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro. > (HAVE_PRE_MODIFY_DISP): Likewise. > * config/riscv/riscv.md (zero_extendqi2): Disable > for XTheadMemIdx. > (*zero_extendqi2_internal): Convert to expand, > create INSN with same name and disable it for XTheadMemIdx. > (extendsidi2): Likewise. > (*extendsidi2_internal): Disable for XTheadMemIdx. > * config/riscv/thead-peephole.md: Add helper peephole passes. > * config/riscv/thead.cc (valid_signed_immediate): New helper > function. > (th_memidx_classify_address_modify): New function. > (th_memidx_legitimate_modify_p): Likewise. > (th_memidx_output_modify): Likewise. > (is_memidx_mode): Likewise. > (th_memidx_classify_address_index): Likewise. > (th_memidx_legitimate_index_p): Likewise. > (th_memidx_output_index): Likewise. > (th_classify_address): Likewise. > (th_output_move): Likewise. > (th_print_operand_address): Likewise. > * config/riscv/thead.md (*th_memidx_mov2): > New INSN. > (*th_memidx_zero_extendqi2): Likewise. > (*th_memidx_extendsidi2): Likewise > (*th_memidx_zero_extendsidi2): Likewise. > (*th_memidx_zero_extendhi2): Likewise. > (*th_memidx_extend2): Likewise > (*th_memidx_bb_zero_extendsidi2): Likewise. > (*th_memidx_bb_zero_extendhi2): Likewise. > (*th_memidx_bb_extendhi2): Likewise. > (*th_memidx_bb_extendqi2): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadmemidx-helpers.h: New test. > * gcc.target/riscv/xtheadmemidx-index-update.c: New test. > * gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c: New test. > * gcc.target/riscv/xtheadmemidx-index-xtheadbb.c: New test. > * gcc.target/riscv/xtheadmemidx-index.c: New test. > * gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c: New test. > * gcc.target/riscv/xtheadmemidx-modify.c: New test. > * gcc.target/riscv/xtheadmemidx-uindex-update.c: New test. > * gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c: New test. > * gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c: New test. > * gcc.target/riscv/xtheadmemidx-uindex.c: New test. > > diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md > index 5b829b5b968..2a4c734a220 100644 > --- a/gcc/config/riscv/thead-peephole.md > +++ b/gcc/config/riscv/thead-peephole.md > @@ -72,3 +72,217 @@ (define_peephole2 > { > th_mempair_order_operands (operands, true, SImode); > }) > + > +;; All modes that are supported by XTheadMemIdx > +(define_mode_iterator TH_M_ANY [QI HI SI (DI "TARGET_64BIT")]) > + > +;; All non-extension modes that are supported by XTheadMemIdx > +(define_mode_iterator TH_M_NOEXT [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) > + > +;; XTheadMemIdx overview: > +;; All peephole passes attempt to improve the operand utilization of > +;; XTheadMemIdx instructions, where one sign or zero extended > +;; register-index-operand can be shifted left by a 2-bit immediate. > +;; > +;; The basic idea is the following optimization: > +;; (set (reg 0) (op (reg 1) (imm 2))) > +;; (set (reg 3) (mem (plus (reg 0) (reg 4))) > +;; ==> > +;; (set (reg 3) (mem (plus (reg 4) (op2 (reg 1) (imm 2)))) > +;; This optimization only valid if (reg 0) has no further uses. Couldn't this be done by combine if you created define_insn patterns rather than define_peephole2 patterns? Similarly for the other cases handled here. Do you need to define HAVE_{PRE,POST}_MODIFY? I see HAVE_{PRE,POST}_MODIFY_DISP. is defined. If that's sufficient, great. This stuff seems to have changed since I last looked at it. So I have to ask. Is the extension documented? If so, we probably should have a link to it. What's the status of hardware availablity with this extension? Jeff