From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 15B3F3858D35 for ; Thu, 12 Jan 2023 16:51:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 15B3F3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30CGiM8V000400; Thu, 12 Jan 2023 16:51:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=D7MKUn70wMkDmmwa8aHBDLMaFLOg+6gOqxuJqQv4ylY=; b=avMrg7XafgdIcJQbezcu0IkiIdW0Uk/RQmtcu8BD5/pMaUCfrfL7o3AjCLYY1LWZjjyM 95wHhe/PKgMR6Umn39kLbZ4gXTmbghmtDVamOwj++XT7QnW/M8cvvqq0BwDCak8xNCM2 ar/IApnqGycW091P0wwbzuWN5AqCuPKdUhspaZRnmjlZqfXHXhf69cO5bB0E+zKVrjd/ e6WOVO1oc28Ar1xRirIf/NGGlFiJ84HGKNkLnWWwms9mMMg0RUL2/fyQfqSr+azRicyg 7nwEo3kRXuRIPSYlel4oKroLSWV1ZMR1o7wb2/3Iy3QkLv8FLk7qeClKXgEyxx8L6xf+ gQ== Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3n2p08r3r7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Jan 2023 16:51:40 +0000 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 30CEiKvX019887; Thu, 12 Jan 2023 16:51:39 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([9.208.129.118]) by ppma02dal.us.ibm.com (PPS) with ESMTPS id 3n1k8451wm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Jan 2023 16:51:39 +0000 Received: from smtpav01.dal12v.mail.ibm.com (smtpav01.dal12v.mail.ibm.com [10.241.53.100]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 30CGpbx352035940 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 12 Jan 2023 16:51:37 GMT Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 71C375805D; Thu, 12 Jan 2023 16:51:37 +0000 (GMT) Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0B64558057; Thu, 12 Jan 2023 16:51:36 +0000 (GMT) Received: from [9.43.112.208] (unknown [9.43.112.208]) by smtpav01.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 12 Jan 2023 16:51:35 +0000 (GMT) Message-ID: Date: Thu, 12 Jan 2023 22:21:34 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: [PING] [PATCH] swap: Fix incorrect lane extraction by vec_extract() [PR106770] Content-Language: en-US To: GCC Patches Cc: Peter Bergner , Segher Boessenkool , meissner@linux.ibm.com References: From: Surya Kumari Jangala In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ZPejaUEj9Lnnaewhmi5G3vfrzXorf__G X-Proofpoint-ORIG-GUID: ZPejaUEj9Lnnaewhmi5G3vfrzXorf__G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-12_08,2023-01-12_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 malwarescore=0 bulkscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301120120 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping On 04/01/23 1:58 pm, Surya Kumari Jangala via Gcc-patches wrote: > swap: Fix incorrect lane extraction by vec_extract() [PR106770] > > In the routine rs6000_analyze_swaps(), special handling of swappable > instructions is done even if the webs that contain the swappable > instructions are not optimized, i.e., the webs do not contain any > permuting load/store instructions along with the associated register > swap instructions. Doing special handling in such webs will result in > the extracted lane being adjusted unnecessarily for vec_extract. > > Modifying swappable instructions is also incorrect in webs where > loads/stores on quad word aligned addresses are changed to lvx/stvx. > Similarly, in webs where swap(load(vector constant)) instructions are > replaced with load(swapped vector constant), the swappable > instructions should not be modified. > > 2023-01-04 Surya Kumari Jangala > > gcc/ > PR rtl-optimization/106770 > * rs6000-p8swap.cc (rs6000_analyze_swaps): . > > gcc/testsuite/ > PR rtl-optimization/106770 > * gcc.target/powerpc/pr106770.c: New test. > --- > > diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc > index 19fbbfb67dc..7ed39251df9 100644 > --- a/gcc/config/rs6000/rs6000-p8swap.cc > +++ b/gcc/config/rs6000/rs6000-p8swap.cc > @@ -179,6 +179,9 @@ class swap_web_entry : public web_entry_base > unsigned int special_handling : 4; > /* Set if the web represented by this entry cannot be optimized. */ > unsigned int web_not_optimizable : 1; > + /* Set if the web represented by this entry has been optimized, ie, > + register swaps of permuting loads/stores have been removed. */ > + unsigned int web_is_optimized : 1; > /* Set if this insn should be deleted. */ > unsigned int will_delete : 1; > }; > @@ -2627,22 +2630,43 @@ rs6000_analyze_swaps (function *fun) > /* For each load and store in an optimizable web (which implies > the loads and stores are permuting), find the associated > register swaps and mark them for removal. Due to various > - optimizations we may mark the same swap more than once. Also > - perform special handling for swappable insns that require it. */ > + optimizations we may mark the same swap more than once. Fix up > + the non-permuting loads and stores by converting them into > + permuting ones. */ > for (i = 0; i < e; ++i) > if ((insn_entry[i].is_load || insn_entry[i].is_store) > && insn_entry[i].is_swap) > { > swap_web_entry* root_entry > = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); > - if (!root_entry->web_not_optimizable) > + if (!root_entry->web_not_optimizable) { > mark_swaps_for_removal (insn_entry, i); > + root_entry->web_is_optimized = true; > + } > } > - else if (insn_entry[i].is_swappable && insn_entry[i].special_handling) > + else if (insn_entry[i].is_swappable > + && (insn_entry[i].special_handling == SH_NOSWAP_LD || > + insn_entry[i].special_handling == SH_NOSWAP_ST)) > + { > + swap_web_entry* root_entry > + = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); > + if (!root_entry->web_not_optimizable) { > + handle_special_swappables (insn_entry, i); > + root_entry->web_is_optimized = true; > + } > + } > + > + /* Perform special handling for swappable insns that require it. > + Note that special handling should be done only for those > + swappable insns that are present in webs optimized above. */ > + for (i = 0; i < e; ++i) > + if (insn_entry[i].is_swappable && insn_entry[i].special_handling && > + !(insn_entry[i].special_handling == SH_NOSWAP_LD || > + insn_entry[i].special_handling == SH_NOSWAP_ST)) > { > swap_web_entry* root_entry > = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); > - if (!root_entry->web_not_optimizable) > + if (root_entry->web_is_optimized) > handle_special_swappables (insn_entry, i); > } > > diff --git a/gcc/testsuite/gcc.target/powerpc/pr106770.c b/gcc/testsuite/gcc.target/powerpc/pr106770.c > new file mode 100644 > index 00000000000..84e9aead975 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr106770.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_p8vector_ok } */ > +/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ > +/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */ > + > +/* Test case to resolve PR106770 */ > + > +#include > + > +int cmp2(double a, double b) > +{ > + vector double va = vec_promote(a, 1); > + vector double vb = vec_promote(b, 1); > + vector long long vlt = (vector long long)vec_cmplt(va, vb); > + vector long long vgt = (vector long long)vec_cmplt(vb, va); > + vector signed long long vr = vec_sub(vlt, vgt); > + > + return vec_extract(vr, 1); > +} > +