From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.14]) by sourceware.org (Postfix) with UTF8SMTPS id 349083856241 for ; Wed, 24 May 2023 09:41:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 349083856241 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921279; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=47q9iI4Jv+t2/c57MqvrE7+PNXqp3XEtOFaM+gox4xk=; b=CD4PnVhyOuFVIec7fFUEMt5EAvR8gJTpdU9vQ/ZWdRS5nbS5hBmY7Hp5F9yJ1u2LuuhUWp f3oMa/WrWa3RPemHiJSSFel8uZayf9kgzFVs2RVYGYcZXYke0wlve7ibopryKASd8rbQcb o7dejyDALXwfA+EZyrqCPF8ld5wn1Ld5ndErYQRNjbRDmOh5zjnv7ZxuBrvyQqqFWVUp4F alMfhtQRVU7f0CGQYa3LnqbMp2BmEWdPip2JYfC1nlZHqm7BchCPVVPv5UYc2i2z5oKAEE GSCuiVHd2E0sZZQVf6/64utC3LHTC1qmHIaDkSnYGsJ+FGiG5y3tpzaKWSRf3A== Cc: "YunQiang Su" , "Maciej W . Rozycki" Message-Id: Mime-Version: 1.0 In-Reply-To: From: "Jie Mei" Content-Transfer-Encoding: 8bit References: X-Mailer: git-send-email 2.40.1 To: Subject: [PATCH v3 5/9] MIPS: Add LUI instruction for mips16e2 Date: Wed, 24 May 2023 17:41:18 +0800 X-Lms-Return-Path: Content-Type: multipart/alternative; boundary=e84fdfc9cb1fad511cb74342060e56b9dd3eba92362a6df81500bad0ddb9 X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_ADSP_NXDOMAIN,DKIM_INVALID,DKIM_SIGNED,GIT_PATCH_0,HTML_MESSAGE,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,KAM_STOCKGEN,NO_DNS_FOR_FROM,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --e84fdfc9cb1fad511cb74342060e56b9dd3eba92362a6df81500bad0ddb9 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same as above. * config/mips/mips.md: Same as above gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Add new tests for mips16e2. --- gcc/config/mips/mips.cc | 44 ++++++++++++++++++------ gcc/config/mips/mips.md | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 22 ++++++++++++ 3 files changed, 56 insertions(+), 12 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index d86911d10c2..0792f89cab4 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2295,7 +2295,9 @@ mips_symbol_insns_1 (enum mips_symbol_type type, mach= ine_mode mode) The final address is then $at + %lo(symbol). With 32-bit symbols we just need a preparatory LUI for normal mode and a preparatory LI and SLL for MIPS16. */ - return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; + return ABI_HAS_64BIT_SYMBOLS=20 + ? 6=20 + : (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? 3 : 2; =20 case SYMBOL_GP_RELATIVE: /* Treat GP-relative accesses as taking a single instruction on @@ -2867,7 +2869,7 @@ mips_const_insns (rtx x) =20 /* This is simply an LUI for normal mode. It is an extended LI followed by an extended SLL for MIPS16. */ - return TARGET_MIPS16 ? 4 : 1; + return TARGET_MIPS16 ? (ISA_HAS_MIPS16E2 ? 2 : 4) : 1; =20 case CONST_INT: if (TARGET_MIPS16) @@ -2879,7 +2881,10 @@ mips_const_insns (rtx x) : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 : IN_RANGE (-INTVAL (x), 0, 255) ? 2 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 - : 0); + : ISA_HAS_MIPS16E2 + ? (trunc_int_for_mode (INTVAL (x), SImode) =3D=3D INTVAL (x) + ? 4 : 8) + : 0); =20 return mips_build_integer (codes, INTVAL (x)); =20 @@ -5252,6 +5257,11 @@ mips_output_move (rtx dest, rtx src) if (!TARGET_MIPS16) return "li\t%0,%1\t\t\t# %X1"; =20 + if (ISA_HAS_MIPS16E2 + && LUI_INT (src) + && !SMALL_OPERAND_UNSIGNED (INTVAL (src))) + return "lui\t%0,%%hi(%1)\t\t\t# %X1"; + if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) return "li\t%0,%1"; =20 @@ -5260,7 +5270,7 @@ mips_output_move (rtx dest, rtx src) } =20 if (src_code =3D=3D HIGH) - return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; + return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; =20 if (CONST_GP_P (src)) return "move\t%0,%1"; @@ -11983,13 +11993,25 @@ mips_output_function_prologue (FILE *file) { if (TARGET_MIPS16) { - /* This is a fixed-form sequence. The position of the - first two instructions is important because of the - way _gp_disp is defined. */ - output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); - output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); - output_asm_insn ("sll\t$2,16", 0); - output_asm_insn ("addu\t$2,$3", 0); + if (ISA_HAS_MIPS16E2) + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("lui\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("addu\t$2,$3", 0); + } + else + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("sll\t$2,16", 0); + output_asm_insn ("addu\t$2,$3", 0); + } } else { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 9f652310aa2..73c9acd484f 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4634,7 +4634,7 @@ (define_split [(set (match_operand:P 0 "d_operand") (high:P (match_operand:P 1 "symbolic_operand_with_high")))] - "TARGET_MIPS16 && reload_completed" + "TARGET_MIPS16 && reload_completed && !ISA_HAS_MIPS16E2" [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) =20 diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.t= arget/mips/mips16e2.c index ce8b4f1819b..780891b4056 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -100,3 +100,25 @@ test08 (unsigned int a) return ((a + 0x2) ^ 0x3f0); } =20 +/* Test LUI. */ + +/* { dg-final { scan-assembler "test09:.*\tlui\t.*test09\n" } } */ +int +test09 (void) +{ + return 0x44440000; +} + +/* Test LUI relocation sequence chang. */ + +/* { dg-final { scan-assembler "test10:.*\tlui\t.*test10\n" } } */ +int *a10; + +int +test10 (int i) +{ + a10 =3D &i; + *a10 =3D 0x44440000; + return i; +} + --=20 2.40.1= --e84fdfc9cb1fad511cb74342060e56b9dd3eba92362a6df81500bad0ddb9--