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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id mh16-20020a170906eb9000b0096f7ae359a5sm10403174ejb.30.2023.06.16.02.21.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jun 2023 02:21:58 -0700 (PDT) Message-ID: Date: Fri, 16 Jun 2023 11:21:57 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com, rguenther@suse.de, richard.sandiford@arm.com Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs Content-Language: en-US To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org References: <20230615131435.10323-1-juzhe.zhong@rivai.ai> From: Robin Dapp In-Reply-To: <20230615131435.10323-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Juzhe, > +@cindex @code{len_maskload@var{m}@var{n}} instruction pattern > +@item @samp{len_maskload@var{m}@var{n}} > +Perform a masked load (operand 2 - operand 4) elements from vector memory > +operand 1 into vector register operand 0, setting the other elements of > +operand 0 to undefined values. This is a combination of len_load and maskload. > +Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 2 > +has whichever integer mode the target prefers. A secondary mask is specified in > +operand 3 which must be of type @var{n}. Operand 4 conceptually has mode @code{QI}. > + > +Operand 2 can be a variable or a constant amount. Operand 4 specifies a > +constant bias: it is either a constant 0 or a constant -1. The predicate on > +operand 4 must only accept the bias values that the target actually supports. > +GCC handles a bias of 0 more efficiently than a bias of -1. > + > +If (operand 2 - operand 4) exceeds the number of elements in mode > +@var{m}, the behavior is undefined. > + > +If the target prefers the length to be measured in bytes > +rather than elements, it should only implement this pattern for vectors > +of @code{QI} elements. > + > +This pattern is not allowed to @code{FAIL}. Please still change "Perform a masked load (operand 2 - operand 4) elements" to "Perform a masked load of (operand 2 + operand 4) elements". "vector memory operand" -> "memory operand" As Richi has mentioned we are adding the negative bias not subtracting a positive one. You could also change the len_load and len_store comments while at it so as to not introduce more confusion. The "secondary" can also be omitted now because we don't have a primary mask somewhere. Maybe, for clarification, even if it's implicit: "A mask is specified in operand 3 which must... The mask has lower precedence than the length and is itself subject to length masking, i.e. only mask indices <= (operand 2 + operand 4) are used." > + > +@cindex @code{len_maskstore@var{m}@var{n}} instruction pattern > +@item @samp{len_maskstore@var{m}@var{n}} > +Perform a masked store (operand 2 - operand 4) vector elements from vector register > +operand 1 into memory operand 0, leaving the other elements of operand 0 unchanged. > +This is a combination of len_store and maskstore. > +Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 2 has whichever > +integer mode the target prefers. A secondary mask is specified in operand 3 which must be > +of type @var{n}. Operand 4 conceptually has mode @code{QI}. Same thing applies here "store of (operand 2 + operand 4) vector elements as well as the secondary. Thanks. No V5 necessary IMHO for those but let's see what Richard says. Regards Robin