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From: Jeff Law <jlaw@ventanamicro.com>
To: Xi Ruoyao <xry111@xry111.site>, Jiawei <jiawei@iscas.ac.cn>,
	gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@dabbelt.com,
	christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn,
	shihua@iscas.ac.cn, shiyulong@iscas.ac.cn,
	chenyixuan@iscas.ac.cn
Subject: Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)
Date: Mon, 25 Mar 2024 13:59:14 -0600	[thread overview]
Message-ID: <af9b99ce-26d8-4dc1-b471-21ee716d463e@ventanamicro.com> (raw)
In-Reply-To: <23afe5bfa6bea4e52c2fef15a615112208f06c98.camel@xry111.site>



On 3/25/24 1:48 PM, Xi Ruoyao wrote:
> On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote:
>>> +/* Costs to use when optimizing for xiangshan nanhu.  */
>>> +static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
>>> +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},	/* fp_add */
>>> +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},	/* fp_mul */
>>> +  {COSTS_N_INSNS (10), COSTS_N_INSNS (20)},	/* fp_div */
>>> +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},	/* int_mul */
>>> +  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},	/* int_div */
>>> +  6,						/* issue_rate */
>>> +  3,						/* branch_cost */
>>> +  3,						/* memory_cost */
>>> +  3,						/* fmv_cost */
>>> +  true,						/* slow_unaligned_access */
>>> +  false,					/* use_divmod_expansion */
>>> +  RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH,          /* fusible_ops */
>>> +  NULL,						/* vector cost */
> 
>> Is your integer division really that fast?  The table above essentially
>> says that your cpu can do integer division in 6 cycles.
> 
> Hmm, I just seen I've coded some even smaller value for LoongArch CPUs
> so forgive me for "hijacking" this thread...
> 
> The problem seems integer division may spend different number of cycles
> for different inputs: on LoongArch LA664 I've observed 5 cycles for some
> inputs and 39 cycles for other inputs.
> 
> So should we use the minimal value, the maximum value, or something in-
> between for TARGET_RTX_COSTS and pipeline descriptions?
Yea, early outs are relatively common in the actual hardware 
implementation.

The biggest reason to refine the cost of a division is so that we've got 
a reasonably accurate cost for division by a constant -- which can often 
be done with multiplication by reciprocal sequence.  The multiplication 
by reciprocal sequence will use mult, add, sub, shadd insns and you need 
a reasonable cost model for those so you can compare against the cost of 
a hardware division.

So to answer your question.  Choose something sensible, you probably 
don't want the fastest case and you may not want the slowest case.

Jeff

  reply	other threads:[~2024-03-25 19:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-27  8:52 [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture Jiawei
2024-03-19  2:54 ` Jeff Law
2024-03-19 12:43   ` jiawei
2024-03-25 19:48   ` TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.) Xi Ruoyao
2024-03-25 19:59     ` Jeff Law [this message]
2024-03-25 20:13       ` Palmer Dabbelt
2024-03-25 20:27         ` Jeff Law
2024-03-25 20:31           ` Palmer Dabbelt
2024-03-25 20:49             ` Jeff Law
2024-03-25 20:57               ` Palmer Dabbelt
2024-03-25 21:41                 ` Jeff Law

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