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Subject: Re: [PATCH] LoongArch: Enable shrink wrapping
To: Lulu Cheng <chenglulu@loongson.cn>, Xi Ruoyao <xry111@xry111.site>,
 gcc-patches@gcc.gnu.org
Cc: WANG Xuerui <i@xen0n.name>, Chenghua Xu <xuchenghua@loongson.cn>
References: <20230423131903.155998-1-xry111@xry111.site>
 <c73e3193-fb24-d665-ff44-03f9f6a98a18@loongson.cn>
From: Guo Jie <guojie@loongson.cn>
Message-ID: <afdbf9a0-07ee-1ef6-7e73-f337e5ace3cd@loongson.cn>
Date: Tue, 25 Apr 2023 17:12:57 +0800
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/* snip */

>>   diff --git a/gcc/testsuite/gcc.target/loongarch/shrink-wrap.c 
>> b/gcc/testsuite/gcc.target/loongarch/shrink-wrap.c
>> new file mode 100644
>> index 00000000000..f2c867a2769
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/loongarch/shrink-wrap.c
>> @@ -0,0 +1,22 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O -fshrink-wrap" } */
>> +
>> +/* f(x) should do nothing if x is 0.  */
>> +/* { dg-final { scan-assembler "bnez\t\\\$r4,\[^\n\]*\n\tjr\t\\\$r1" 
>> } } */
>> +
>> +void g(void);
>> +
>> +void
>> +f(int x)
>> +{
>> +  if (x)
>> +    {
>> +      register int s0 asm("s0") = x;
>> +      register int s1 asm("s1") = x;
>> +      register int s2 asm("s2") = x;
>> +      asm("" : : "r"(s0));
>> +      asm("" : : "r"(s1));
>> +      asm("" : : "r"(s2));
>> +      g();
>> +    }
>> +}

I think the test case cannot fully reflect the optimization effect of 
the current patch,

because even without the patch, -O -fshrink-wrap will still perform 
architecture independent optimization.

This patch considers architecture related registers as finer grained 
optimization for shrink wrapping,

I think a test case like the one below is more suitable:


int foo(int x)
{
   if (x)
   {
     __asm__ ("":::"s0","s1");
     return x;
   }

   __asm__ ("":::"s2","s3");
   return 0;
}

Otherwise LGTM, thanks!