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Tue, 19 Dec 2023 21:38:42 -0800 (PST) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id n1-20020a5ed901000000b00786cf14a8absm6643492iop.43.2023.12.19.21.38.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Dec 2023 21:38:42 -0800 (PST) Message-ID: Date: Tue, 19 Dec 2023 22:38:41 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension Content-Language: en-US To: Sergei Lewis , gcc-patches@gcc.gnu.org References: <20231219095348.356551-1-slewis@rivosinc.com> <20231219095348.356551-3-slewis@rivosinc.com> From: Jeff Law In-Reply-To: <20231219095348.356551-3-slewis@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 12/19/23 02:53, Sergei Lewis wrote: > gcc/ChangeLog > > * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New function > declaration. > > * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New > function: this generates an inline vectorised memory set, if and only if we > know the entire operation can be performed in a single vector store > > * config/riscv/riscv.md (setmem): Try riscv_vector::expand_vec_setmem > for constant lengths > > gcc/testsuite/ChangeLog > * gcc.target/riscv/rvv/base/setmem-1.c: New tests > * gcc.target/riscv/rvv/base/setmem-2.c: New tests > * gcc.target/riscv/rvv/base/setmem-3.c: New tests As with patch 1/3 this needs to be regression tested. The other concern, which I should have voiced with patch 1/3 is that this was submitted after the gcc-14 development window closed. While we do have some degrees of freedom to accept backend specific new features, we really shouldn't be adding new features/optimizations at this point. We really should just be fixing bugs and new features should be queued for gcc-15. > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 1b3f66fd15c..dd34211ca80 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -2387,6 +2387,20 @@ > FAIL; > }) > > +(define_expand "setmemsi" > + [(set (match_operand:BLK 0 "memory_operand") ;; Dest > + (match_operand:QI 2 "nonmemory_operand")) ;; Value > + (use (match_operand:SI 1 "const_int_operand")) ;; Length > + (match_operand:SI 3 "const_int_operand")] ;; Align > + "TARGET_VECTOR" > +{ > + if (riscv_vector::expand_vec_setmem (operands[0], operands[1], operands[2], > + operands[3])) > + DONE; > + else > + FAIL; > +}) Is the :SI really needed for operands1 and operands3? a CONST_INT node never has a mode. Or is the existence of the mode just to keep the gen* programs from generating a warning? And if we're going to keep a mode, particularly on the length, shouldn't the length be in mode P? Jeff