[PATCH] RISC-V: Standardize formatting of SFB ALU conditional move

["Maciej W. Rozycki" <macro@embecosm.com>]

Standardize the formatting of SFB ALU conditional move operations from:

	beq a2,zero,1f; mv a0,zero; 1: # movcc

to:

	beq	a2,zero,1f	# movcc
	mv	a0,zero
1:

for consistency with other assembly code produced.  No functional change.

	gcc/
	* gcc/config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc): Fix 
	output pattern formatting.
---
Hi,

 No regressions in `-mtune=sifive-7-series' testing except for:

FAIL: gcc.target/riscv/pr105314.c   -O0   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -O1   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -O2   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -O3 -g   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -Os   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none   scan-assembler-not \tbeq\t
FAIL: gcc.target/riscv/pr105314.c   -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-not \tbeq\t

as expected due to the brokenness of the test case, as discussed here: 
<https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598542.html> (still 
unresolved).

 OK to apply?

  Maciej
---
 gcc/config/riscv/riscv.md |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

gcc-riscv-movcc-format.diff
Index: gcc/gcc/config/riscv/riscv.md
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.md
+++ gcc/gcc/config/riscv/riscv.md
@@ -2187,8 +2187,8 @@
 	 (match_operand:GPR 4 "sfb_alu_operand" "rJ,IL")))]
   "TARGET_SFB_ALU"
   "@
-   b%C5 %1,%z2,1f; mv %0,%z4; 1: # movcc
-   b%C5 %1,%z2,1f; li %0,%4; 1: # movcc"
+   b%C5\t%1,%z2,1f\t# movcc\;mv\t%0,%z4\n1:
+   b%C5\t%1,%z2,1f\t# movcc\;li\t%0,%4\n1:"
   [(set_attr "length" "8")
    (set_attr "type" "sfb_alu")
    (set_attr "mode" "<GPR:MODE>")])