From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id BDD57385828D for ; Sun, 19 Nov 2023 05:41:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BDD57385828D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BDD57385828D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::62b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372489; cv=none; b=Uc/Xl/8kWB7rHXKjC8VnlOkfAJLhtEZzrSZ/Nz2U5z6dhgA9nEET0WCQzVEf1a6NdkkpBMN/3P7i6FZAWV0J42RYarLfP2Bh13KD3Xat+WeVwMF4nEg1z0xBJ4+ZfMDT1HtsjAhMvaU4Sx406WwYTA6cdRaNOHtFxaHX1/Ngn10= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372489; c=relaxed/simple; bh=/WjzrJZrFnId7fr8PHu0QTYZsEpSLmVAs5d4D5BuzS0=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=q90WqueyoNyR04LSHeIN40CxIFh0vKpEF3BHcyIEBPT2HW+BZhaDhY4mDmB1bsLCQbpgoku2+XccuhWhHH+z9wTbEKweIybwwWmGvkI9oeiQzQYH8jIvwm+86Fno0gtUo/RnHfRNgRCh3c4/Y3dFidv5/d0Fg+XklYqb6//VxPQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-9db6cf8309cso435828666b.0 for ; Sat, 18 Nov 2023 21:41:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1700372486; x=1700977286; darn=gcc.gnu.org; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=8IChBDQyNqs9L/5jI7kXNuu2heirprWAAjtNHKLHBJw=; b=hfD1R5qbAi/pB0b5zb5TMdCCSWXQT/zYzktorqT+oVsF3mHO1AKiAYLgwTkaDKl1X5 1yL6iuTqcJr0BtowYCIVT44TngKb0dEV8Xde+mAmOVEHXEU/ti/l+7Vx7wkeqyw8qK4o fuo4ZxpZWgW+w/SmQP7wyYFDYlSaw+jWaaBj+ukYtb7HwjVhfA3bS0IpissamTCxl66U bWZrlHS/ns8O8sJliXgKkKE18U/mn2TYvhkbGFagpXY+Pl93NMSkOXdCg8zPi162uC0X P2XLJXXBfSUEmuCjnukzeDqvupta80yRHqqgFaOi39RZm5P3+0hwAmDIsm981axdJ09O 2vRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700372486; x=1700977286; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=8IChBDQyNqs9L/5jI7kXNuu2heirprWAAjtNHKLHBJw=; b=s/049elAZD2x5Z5plqeTIA+/ZG9z1kS75UHBcYLEPDYtNYbKAIQx9jL9sa4jCJQA3a nWqigKIhVGXsVZKWH1tIgy34FtlFE2IfcPeczfIXl6iIi1cqEGwMY8OAFP7fJAogWqF/ QbPUy00vNkdR7/g1CtDOLXBTP5RciznKW0ICSOvJ+KBhjUaQuSl/tG9PXMb7Qmkg26lV FOzKXnKGWzx9HOd1FlyByZ3N6NvHgZHy6AEStd/xxb2BYdbPmUzvHJ7/GN98fLT9dLyf +K8AKt0cTVBn7CxKLL87c0pWSqtDdzZlJ/ed5fWTebD39s2ShIhBTxUjDN9Nc61UrRs8 XPQQ== X-Gm-Message-State: AOJu0Yy4fPWzTa1IIaY91h9GPYTR/hFUlR7iaGQ/7LPSL5xFnVmmdE+S dvYlUpuIXrgqL6FXKgEaAkhbRE+2iF+Av7oYkbAk+g== X-Google-Smtp-Source: AGHT+IFB3fH3qcZrJ9iy+1YJl3NHDbPqMEU75eJG09GkapnOCvIFKhRd5P4QK2lmzHpoIAAAu8P0oA== X-Received: by 2002:a17:906:1017:b0:9fd:b304:c7a3 with SMTP id 23-20020a170906101700b009fdb304c7a3mr53160ejm.44.1700372486544; Sat, 18 Nov 2023 21:41:26 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id s23-20020a170906bc5700b009fca9f39e98sm412712ejv.26.2023.11.18.21.41.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Nov 2023 21:41:26 -0800 (PST) Date: Sun, 19 Nov 2023 05:41:24 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 29/44] RISC-V: Add `addMODEcc' implementation for generic targets In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Provide RTL expansion of conditional-add operations for generic targets using a suitable sequence of base integer machine instructions according to cost evaluation by if-conversion. Use existing `-mmovcc' command line option to enable this transformation. gcc/ * config/riscv/riscv.md (addcc): New expander. --- gcc/config/riscv/riscv.md | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -2655,6 +2655,8 @@ [(set_attr "type" "branch") (set_attr "mode" "none")]) +;; Conditional move and add patterns. + (define_expand "movcc" [(set (match_operand:GPR 0 "register_operand") (if_then_else:GPR (match_operand 1 "comparison_operator") @@ -2670,6 +2672,45 @@ FAIL; }) +(define_expand "addcc" + [(match_operand:GPR 0 "register_operand") + (match_operand 1 "comparison_operator") + (match_operand:GPR 2 "arith_operand") + (match_operand:GPR 3 "arith_operand")] + "TARGET_MOVCC" +{ + rtx cmp = operands[1]; + rtx cmp0 = XEXP (cmp, 0); + rtx cmp1 = XEXP (cmp, 1); + machine_mode mode0 = GET_MODE (cmp0); + + /* We only handle word mode integer compares for now. */ + if (INTEGRAL_MODE_P (mode0) && mode0 != word_mode) + FAIL; + + enum rtx_code code = GET_CODE (cmp); + rtx reg0 = gen_reg_rtx (mode); + rtx reg1 = gen_reg_rtx (mode); + rtx reg2 = gen_reg_rtx (mode); + bool invert = false; + + if (INTEGRAL_MODE_P (mode0)) + riscv_expand_int_scc (reg0, code, cmp0, cmp1, &invert); + else if (FLOAT_MODE_P (mode0) && fp_scc_comparison (cmp, GET_MODE (cmp))) + riscv_expand_float_scc (reg0, code, cmp0, cmp1); + else + FAIL; + + if (invert) + riscv_emit_binary (PLUS, reg1, reg0, constm1_rtx); + else + riscv_emit_unary (NEG, reg1, reg0); + riscv_emit_binary (AND, reg2, reg1, operands[3]); + riscv_emit_binary (PLUS, operands[0], reg2, operands[2]); + + DONE; +}) + ;; Patterns for implementations that optimize short forward branches. (define_insn "*movcc"