From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id B00F5385C405 for ; Sun, 19 Nov 2023 05:43:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B00F5385C405 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B00F5385C405 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::634 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372620; cv=none; b=mCRnuIxICQBVlJcQHcWC1pgnviWguhI9xpw3hmE3lMngRux+UrvWbmaZkFvwdsdD8w/CAddi5p6+VIetNhZDfeCbsh/fwwgAU/xdks2egdaViz/IpMiYqk7m2OtP2w06gEdkxYqy7wmcoyuSoPO8UBR1CBSBnQnm5kq5nyW+tss= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372620; c=relaxed/simple; bh=pTuhKbGCN0BcOQCpv0CuTAhCZQxdxh9d/Dl1SQNJGmw=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=tCvrEt2j5PWI80HDytbvKbET6nH2s9uN0kmFLhekn3vcRGJcazfaik7juUWv716bm8G8L6KxiD6JGOgUugcEgBReg/5elxFzOSKGHin3cZoA9AQkzEMkwfZLsSaIHXFHVT1bXqt1uIwNRAv3tPhy+xeJOU8xQ4Xl/mK3PCU9m2w= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-9c2a0725825so459538066b.2 for ; Sat, 18 Nov 2023 21:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1700372617; x=1700977417; darn=gcc.gnu.org; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=2edoIH4bbRSESTvYgZHtG6W+yn31nmFlz6JqqA9uPzs=; b=cOP7b5f/7FyWcm46z90tcC59RFqhZqpt5PxnEHsvq0KIg5MAqN2ra+p9sOZxR2asJX +t/SDTzYrjHGONnuXzX1FCope2C2nnasdLkuL7PXvGMAtQSKCOjYeuq5idCEESiXxUtn Fp7Np/SPern0v9SO78P1iuP277tRbZEY/14NvrNRLbivyesl6hFC/gDbmsiOG61uPAQb O+4uqGG1C4apizD7OQ9d8JP1hc/TC2U8SVmnTXWV+ifmauIi+LaE8W6kwTBoeES+mGEe wkt9jEmutRfO0A1DTNHsl37ieVDVpxSt91GEUucBWMyg9yCEz+4vFhLhgRCVuHh13Ojl 07jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700372617; x=1700977417; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=2edoIH4bbRSESTvYgZHtG6W+yn31nmFlz6JqqA9uPzs=; b=SnUEeAyXiU6GdOL8DP/1YhZF/ocISbaFqPpRrYEUYj2n2PrgvT0cblj0o2LxN/MV3f AD30YIhOjvjeIAi+hULAQ9ySZEiijw2HKDN3N/5mew9d8f3KVoge2vnT2hSW06d/iUjs YJTlNWUMAUhTpXP/8sU8+Cwj8CcaAguGsciebweQkYMRzEvSdFvOW5IFEG1xy45sW6Lh VCdN4jcfB+j2yE2w0HHTGVXDDuEvNL/Yulqdx86PixOCoPpVYbIgbXznwQRkOtuP8TCc piVrqk5ocxF05ZSrL35Mx9u1uV2ZA8GMEhnjlCFOmYGODEGYNpY+oQ1P9SUCDi2hBplW Fw2w== X-Gm-Message-State: AOJu0YwFKGHDUy0JIUEbzJe8bafU+oyH0guaMj3jlFz5wPwdkpmng9Fh 9gCvmHW/UFCXa9bQq3heFZEqD8PHMiCtBIrW0nu79A== X-Google-Smtp-Source: AGHT+IHUNdfiKcWLDvIUg7zlDT7l6QrrqLEW/yWf56zUfIJWqAc7MFzV6INVWvjy/YLUC0vOX26FKQ== X-Received: by 2002:a17:906:210:b0:9f7:b852:f807 with SMTP id 16-20020a170906021000b009f7b852f807mr2707778ejd.9.1700372617404; Sat, 18 Nov 2023 21:43:37 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id t9-20020a170906178900b009fd83a7362csm102167eje.70.2023.11.18.21.43.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Nov 2023 21:43:37 -0800 (PST) Date: Sun, 19 Nov 2023 05:43:34 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We have no FNE.fmt machine instructions, but we can emulate them for the purpose of conditional-move and conditional-add operations by using the respective FEQ.fmt instruction and then swapping the data input operands or complementing the mask for the conditional addend respectively, so update our handlers accordingly. gcc/ * config/riscv/riscv-protos.h (riscv_expand_float_scc): Add `invert_ptr' parameter. * config/riscv/riscv.cc (riscv_emit_float_compare): Add NE inversion handling. (riscv_expand_float_scc): Pass `invert_ptr' through to `riscv_emit_float_compare'. (riscv_expand_conditional_move): Pass `&invert' to `riscv_expand_float_scc'. * config/riscv/riscv.md (addcc): Likewise. --- gcc/config/riscv/riscv-protos.h | 3 ++- gcc/config/riscv/riscv.cc | 23 +++++++++++++++-------- gcc/config/riscv/riscv.md | 2 +- 3 files changed, 18 insertions(+), 10 deletions(-) gcc-riscv-emit-float-compare-ne.diff Index: gcc/gcc/config/riscv/riscv-protos.h =================================================================== --- gcc.orig/gcc/config/riscv/riscv-protos.h +++ gcc/gcc/config/riscv/riscv-protos.h @@ -132,7 +132,8 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST #ifdef RTX_CODE extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); -extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); +extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx, + bool *invert_ptr = nullptr); extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x); extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y); Index: gcc/gcc/config/riscv/riscv.cc =================================================================== --- gcc.orig/gcc/config/riscv/riscv.cc +++ gcc/gcc/config/riscv/riscv.cc @@ -3965,7 +3965,8 @@ riscv_emit_int_compare (enum rtx_code *c /* Like riscv_emit_int_compare, but for floating-point comparisons. */ static void -riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1) +riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1, + bool *invert_ptr = nullptr) { rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1; enum rtx_code fp_code = *code; @@ -4029,10 +4030,15 @@ riscv_emit_float_compare (enum rtx_code #undef UNORDERED_COMPARISON case NE: - *code = EQ; - *op0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1); - *op1 = const0_rtx; - break; + fp_code = EQ; + if (invert_ptr != nullptr) + *invert_ptr = !*invert_ptr; + else + { + cmp_op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1); + cmp_op1 = const0_rtx; + } + gcc_fallthrough (); case EQ: case LE: @@ -4078,9 +4084,10 @@ riscv_expand_int_scc (rtx target, enum r /* Like riscv_expand_int_scc, but for floating-point comparisons. */ void -riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) +riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1, + bool *invert_ptr) { - riscv_emit_float_compare (&code, &op0, &op1); + riscv_emit_float_compare (&code, &op0, &op1, invert_ptr); machine_mode mode = GET_MODE (target); if (mode != word_mode) @@ -4171,7 +4178,7 @@ riscv_expand_conditional_move (rtx dest, riscv_expand_int_scc (tmp, code, op0, op1, invert_ptr); else if (FLOAT_MODE_P (mode0) && fp_scc_comparison (op, GET_MODE (op))) - riscv_expand_float_scc (tmp, code, op0, op1); + riscv_expand_float_scc (tmp, code, op0, op1, &invert); else return false; Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -2697,7 +2697,7 @@ if (INTEGRAL_MODE_P (mode0)) riscv_expand_int_scc (reg0, code, cmp0, cmp1, &invert); else if (FLOAT_MODE_P (mode0) && fp_scc_comparison (cmp, GET_MODE (cmp))) - riscv_expand_float_scc (reg0, code, cmp0, cmp1); + riscv_expand_float_scc (reg0, code, cmp0, cmp1, &invert); else FAIL;