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From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: YunQiang Su <yunqiang.su@cipunited.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] MIPS: use 8bit for IPL in Cause register
Date: Wed, 26 Jan 2022 18:40:22 +0000 (GMT)	[thread overview]
Message-ID: <alpine.DEB.2.21.2201261831190.58572@angie.orcam.me.uk> (raw)
In-Reply-To: <20220126032920.1608048-1-yunqiang.su@cipunited.com>

On Wed, 26 Jan 2022, YunQiang Su wrote:

> Since MIPS r2, the IPL section in Cause register has been expand
> to 8bit instead of 6bit.

 Hmm, I cannot see it in my copy of the architecture manual I'm afraid.  
The interpretation may have changed, but the field is still 6-bit (not 
counting the software interrupts).  Now the MCU ASE does expand the IPL 
field, but we can't rely on that here, not at least unconditionally, and 
then MCU is MIPSr3+.

 What problem are you trying to solve anyway?

  Maciej

  reply	other threads:[~2022-01-26 18:40 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-26  3:29 YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki [this message]
2022-02-09  3:18 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU YunQiang Su
2022-02-12  3:54   ` Jeff Law
2022-02-12  8:47     ` Maciej W. Rozycki
2022-03-15  7:00       ` YunQiang Su
2022-03-15  6:51     ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41       ` Maciej W. Rozycki

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