From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: YunQiang Su <yunqiang.su@cipunited.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU
Date: Sat, 12 Feb 2022 08:47:46 +0000 (GMT) [thread overview]
Message-ID: <alpine.DEB.2.21.2202120842330.34636@angie.orcam.me.uk> (raw)
In-Reply-To: <5028ca31-8f20-f26b-13cc-8b3ea6b7ffb8@gmail.com>
On Fri, 11 Feb 2022, Jeff Law wrote:
> > If MIPS MCU extension is enable, the IPL section in Cause register
> > has been expand to 8bit instead of 6bit.
> >
> > gcc/ChangeLog:
> >
> > * config/mips/mips.cc (mips_expand_prologue):
> > IPL is 8bit for MCU ASE.
> OK
But this is still wrong AFAICT.
The mask is applied to the CP0 Status register according to the comment,
but the layout of the interrupt bit-field is different between the CP0
Status and the CP0 Cause registers, so you can't just extract it from one
of the two registers and directly apply to the other.
I would like to know how this code has been verified.
Maciej
next prev parent reply other threads:[~2022-02-12 8:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 3:29 [PATCH] MIPS: use 8bit for IPL in Cause register YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki
2022-02-09 3:18 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU YunQiang Su
2022-02-12 3:54 ` Jeff Law
2022-02-12 8:47 ` Maciej W. Rozycki [this message]
2022-03-15 7:00 ` YunQiang Su
2022-03-15 6:51 ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41 ` Maciej W. Rozycki
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