From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Xi Ruoyao <xry111@mengyan1223.wang>
Cc: Qing Zhao <qing.zhao@oracle.com>,
Richard Sandiford <richard.sandiford@arm.com>,
Jeff Law <law@redhat.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
YunQiang Su <yunqiang.su@cipunited.com>,
Jakub Jelinek <jakub@gcc.gnu.org>
Subject: Re: [PATCH RFC] mips: add TARGET_ZERO_CALL_USED_REGS hook [PR104817, PR104820]
Date: Fri, 1 Apr 2022 15:32:51 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2204011451560.51083@angie.orcam.me.uk> (raw)
In-Reply-To: <b1a497440207cf53d3f733da432ea98f2c94635c.camel@mengyan1223.wang>
On Sat, 12 Mar 2022, Xi Ruoyao via Gcc-patches wrote:
> I'm now thinking: is there always at least one *GPR* which need to be
> cleared? If it's true, let's say GPR $12, and fcc0 & fcc2 needs to be
> cleared, we can use something like:
>
> cfc1 $12, $25
> andi $25, 5
> ctc1 $12, $25
> move $12, $0
There's always $1 ($at) available and we're in a function's epilogue, so
there should be plenty of dead temporaries available as well. For legacy
ISAs you'd need to use the FCSR instead ($31) and two temporaries would be
required as the condition code bits are located in the upper half.
FWIW,
Maciej
prev parent reply other threads:[~2022-04-01 14:32 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 20:40 Xi Ruoyao
2022-03-09 18:25 ` Richard Sandiford
2022-03-10 11:53 ` Xi Ruoyao
2022-03-10 13:41 ` [PATCH v2 " Xi Ruoyao
2022-03-10 13:45 ` [PATCH v2 RFC, resend] " Xi Ruoyao
2022-03-10 20:31 ` [PATCH RFC] " Qing Zhao
2022-03-11 2:54 ` Xi Ruoyao
2022-03-11 16:08 ` Qing Zhao
2022-03-11 17:29 ` Xi Ruoyao
2022-03-11 17:31 ` Xi Ruoyao
2022-03-11 21:26 ` Qing Zhao
2022-03-12 10:48 ` Xi Ruoyao
2022-03-13 6:03 ` Xi Ruoyao
2022-03-14 16:04 ` Richard Sandiford
2022-03-14 17:05 ` Xi Ruoyao
2022-03-16 20:27 ` Qing Zhao
2022-03-18 13:11 ` Xi Ruoyao
2022-03-18 16:09 ` Richard Sandiford
2022-03-18 18:51 ` Qing Zhao
2022-04-01 14:32 ` Maciej W. Rozycki [this message]
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